mc68hc11f1cpu3 Freescale Semiconductor, Inc, mc68hc11f1cpu3 Datasheet - Page 66

• Manufacturer Part Number: mc68hc11f1cpu3
• Description: Mc68hc11f1 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

CR[1:0] — COP Timer Rate Select
5.1.6 CONFIG Register
CONFIG — System Configuration Register
EE[3:0] — EEPROM Mapping Control
Bit 3 — Not implemented
NOCOP — COP System Disable
Bit 1 — Not implemented
EEON — EEPROM Enable
5.2 Effects of Reset
5-4
POR or RESET Pin
Clock Monitor Failure
COP Watchdog Time-out
RESET:
The internal E clock is first divided by 2
These control bits determine a scaling factor for the watchdog timer. Refer to Table 5-
1.
P indicates a previously programmed bit. P(L) indicates that the bit resets to the logic
level held in the latch prior to reset, but the function of COP is controlled by DISR in
TEST1 register.
Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.
Always reads one
Always reads one
Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
reset vector can be fetched from any of six possible locations. Refer to Table 5-2.
These initial states then control on-chip peripheral systems to force them to known
start-up states, as follows:
0 = COP system enabled (forces reset on time-out)
1 = COP system disabled
Bit 7
EE3
Cause of Reset
P
P
1
1
Table 5-2 Reset Cause, Operating Mode, and Reset Vector
EE2
1
1
P
P
6
Freescale Semiconductor, Inc.
For More Information On This Product,
EE1
P
P
5
1
1
RESETS AND INTERRUPTS
Go to: www.freescale.com
EE0
P
P
4
1
1
Normal Mode Vector
15
$FFFC, FFFD
$FFFE, FFFF
$FFFA, FFFB
before it enters the COP watchdog system.
—
3
1
1
1
1
NOCOP
P(L)
P(L)
P
P
2
—
1
1
1
1
1
Special Test or Bootstrap
$BFFC, $BFFD
$BFFE, $BFFF
$BFFA, $BFFB
EEON
Bit 0
TECHNICAL DATA
P
1
1
0
MC68HC11F1
Single Chip
Bootstrap
Expanded
Special Test
$103F