mc68hc11f1cpu3 Freescale Semiconductor, Inc, mc68hc11f1cpu3 Datasheet - Page 120

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mc68hc11f1cpu3

Manufacturer Part Number
mc68hc11f1cpu3
Description
Mc68hc11f1 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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9.4.2 Timer Interrupt Flag Register 2
TFLG2 — Timer Interrupt Flag 2
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Not implemented
9.4.3 Pulse Accumulator Control Register
PACTL — Pulse Accumulator Control
Bit 7 — Not implemented
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
9-14
RESET:
RESET:
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
Clear flags by writing a one to the corresponding bit position(s).
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Always read zero
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits con-
trol the pulse accumulator and IC4/OC5 functions.
Always reads zero
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Bit 7
TOF
Bit 7
0
0
PAEN
RTIF
6
0
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
PAMOD
PAOVF
5
0
5
0
Go to: www.freescale.com
TIMING SYSTEM
PEDGE
PAIF
4
0
4
0
0
0
3
3
I4/O5
2
0
2
0
RTR1
1
0
1
0
TECHNICAL DATA
RTR0
Bit 0
Bit 0
0
0
MC68HC11F1
$1025
$1026

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