mc68hc11f1cpu3 Freescale Semiconductor, Inc, mc68hc11f1cpu3 Datasheet - Page 29

• Manufacturer Part Number: mc68hc11f1cpu3
• Description: Mc68hc11f1 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

3.1.5 Program Counter (PC)
3.1.6 Condition Code Register (CCR)
3.1.6.1 Carry/Borrow (C)
3.1.6.2 Overflow (V)
TECHNICAL DATA
When an interrupt is recognized, the current instruction finishes normally, the return
address (the current value in the program counter) is pushed onto the stack, all of the
CPU registers are pushed onto the stack, and execution continues at the address
specified by the vector for the interrupt. At the end of the interrupt service routine, an
RTI instruction is executed. The RTI instruction causes the saved registers to be pulled
off the stack in reverse order. Program execution resumes at the return address.
There are instructions that push and pull the A and B accumulators and the X and Y
index registers. These instructions are often used to preserve program context. For
example, pushing accumulator A onto the stack when entering a subroutine that uses
accumulator A, and then pulling accumulator A off the stack just before leaving the
subroutine, ensures that the contents of a register will be the same after returning from
the subroutine as it was before starting the subroutine.
The program counter, a 16-bit register, contains the address of the next instruction to
be executed. After reset, the program counter is initialized from one of six possible
vectors, depending on operating mode and the cause of reset.
This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two inter-
rupt masking bits, (I and X) and a stop disable bit (S). In the M68HC11 CPU, condition
codes are automatically updated by most instructions. For example, load accumulator
A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the
N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY),
and transfer/exchange instructions do not affect the condition codes. Refer to Table
3-2, which shows what condition codes are affected by a particular instruction.
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an
arithmetic operation. The C bit also acts as an error flag for multiply and divide opera-
tions. Shift and rotate instructions operate with and through the carry bit to facilitate
multiple-word shift operations.
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V
bit is cleared.
Test or Boot
Normal
Freescale Semiconductor, Inc.
Table 3-1 Reset Vector Comparison
For More Information On This Product,
POR or RESET Pin
$FFFE, F
$BFFE, F
CENTRAL PROCESSING UNIT
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Clock Monitor
$FFFC, D
$BFFC, D
COP Watchdog
$BFFA, B
$FFFA, B
3-5