mc68hc11f1cpu3 Freescale Semiconductor, Inc, mc68hc11f1cpu3 Datasheet - Page 84

• Manufacturer Part Number: mc68hc11f1cpu3
• Description: Mc68hc11f1 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

DDRD — Data Direction Register for Port D
Bits [7:6] — Not implemented
DDD[5:0] — Data Direction for Port D
6.5 Port E
PORTE — Port E Data
6.6 Port F
6-4
RESET:
Alt. Pin
Func.:
RESET:
Always read zero
Port E has eight general-purpose input pins and shares functions with the A/D convert-
er system. When some port E pins are being used for general-purpose input and oth-
ers are being used as A/D inputs, PORTE should not be read during the sample
portion of an A/D conversion.
Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are gen-
eral-purpose outputs. In expanded and test modes, port F pins are low order address
outputs and PORTF is not in the memory map.
0 = Input
1 = Output
Bit 7
Bit 7
AN7
PE7
—
0
I
When the SPI system is in slave mode, DDD5 has no meaning nor
effect. When the SPI system is in master mode, DDD5 determines
whether bit 5 of PORTD is an error detect input (DDD5 = 0) or a gen-
eral-purpose output (DDD5 = 1). If the SPI system is enabled and ex-
pects any of bits [4:2] to be an input, that bit will be an input
regardless of the state of the associated DDR bit. If any of bits [4:2]
are expected to be outputs that bit will be an output only if the asso-
ciated DDR bit is set.
PE6
AN6
—
6
0
6
I
Freescale Semiconductor, Inc.
For More Information On This Product,
DDD5
AN5
PE5
5
0
5
I
PARALLEL INPUT/OUTPUT
Go to: www.freescale.com
DDD4
PE4
AN4
4
0
4
I
NOTE
DDD3
AN3
PE3
0
3
3
I
DDD2
PE2
AN2
2
0
2
I
DDD1
AN1
PE1
1
0
1
I
TECHNICAL DATA
DDD0
Bit 0
Bit 0
PE0
AN0
0
I
MC68HC11F1
$100A
$1009