mc68hc11f1cpu3 Freescale Semiconductor, Inc, mc68hc11f1cpu3 Datasheet - Page 116

• Manufacturer Part Number: mc68hc11f1cpu3
• Description: Mc68hc11f1 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

TCTL1 — Timer Control 1
OM[2:5] — Output Mode
OL[2:5] — Output Level
9.3.7 Timer Interrupt Mask Register 1
TMSK1 — Timer Interrupt Mask 1
OC1I–OC4I — Output Compare x Interrupt Enable
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
IC1I–IC3I — Input Capture x Interrupt Enable
9-10
RESET:
RESET:
These control bit pairs are encoded to specify the action taken after a successful OCx
compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. Refer to
Table 9-3 for the coding.
Use this 8-bit register to enable or inhibit the timer input capture and output compare
interrupts.
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt se-
quence is requested.
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When
I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence
is requested.
OC1I
OM2
Bit 7
Bit 7
0
0
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in
TMSK1 enable the corresponding interrupt sources.
OMx
Table 9-2 Timer Output Compare Configuration
0
0
1
1
OC2I
OL2
6
0
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
OLx
OC3I
OM3
0
1
0
1
5
0
5
0
Go to: www.freescale.com
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
TIMING SYSTEM
OC4I
OL3
4
0
4
0
Action Taken on Successful Compare
NOTE
I4/O5I
OM4
0
0
3
3
OL4
IC1I
2
0
2
0
OM5
IC2I
1
0
1
0
TECHNICAL DATA
Bit 0
Bit 0
OL5
IC3I
0
0
MC68HC11F1
$1020
$1022