mc68hc705c4acfn Freescale Semiconductor, Inc, mc68hc705c4acfn Datasheet
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M68HC05 Microcontrollers WWW.MOTOROLA.COM/SEMICONDUCTORS MC68HC705C4A MC68HSC705C4A Technical Data MC68HC705C4A/D Rev. 3, 5/2002 ...
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MC68HC705C4A MC68HSC705C4A Technical Data To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information ...
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Technical Data Revision Date Level May, 2002 3.0 Corrected World Wide Web address Technical Data 4 Revision History Description MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 Page Number(s) N/A MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A Section 1. General Description . . . . . . . . . . . . . . . . . . . . 21 Section 2. Memory . . . . . . ...
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List of Sections Technical Data 6 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 List of Sections MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.2 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 2.1 2.2 2.3 2.4 2.5 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Section 1. General Description Contents ...
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Table of Contents 2.6 2.7 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 5.1 5.2 Technical Data 8 EPROM/OTPROM (PROM ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Reset Sources . . . . ...
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Table of Contents 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.5 9.5.1 9.5.2 9.5.3 9.6 Technical Data 10 Section 8. Capture/Compare ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Section 10. Serial Communications Interface (SCI) Contents ...
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Table of Contents 11.9 11.9.1 11.9.2 11.9.3 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 12.6 13.1 13.2 13.3 13.4 13.5 Technical Data 12 SPI I/O Registers . . . ...
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Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.11 ...
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Table of Contents A.6 A.7 A.8 A.9 Technical Data 14 3.3-Volt High-Speed Control Timing . . . . . . . . . . . . . . . . . . . . 194 5.0-Volt High-Speed SPI Timing. . ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A Figure 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 5-1 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Title ...
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List of Figures Figure 6-1 6-2 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 9-1 9-2 9-3 9-4 9-5 9-6 Technical Data 16 Title Stop/Wait Mode ...
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Figure 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 14-1 14-2 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Title SCI Data ...
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List of Figures Figure 14-3 14-4 Technical Data 18 Title MC68HC705C4AFN Package Dimensions (Case #777 ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A Table 4-1 7-1 7-2 7-3 9-1 9-2 10-1 10-2 10-3 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 15-1 A-1 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Title Reset/Interrupt Vector Addresses . . . ...
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List of Tables Technical Data 20 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 List of Tables MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.2 1.7.2.1 1.7.2.2 1.7.2.3 1.7.3 1.7.4 1.7.5 1.7.6 1.7.7 1.7.8 1.7.9 1.7.10 1.2 Introduction The MC68HC705C4A is a member of the low-cost, high-performance M68HC05 Family ...
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General Description processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC705C4A is similar to the MC68HC705C8A. The major differences are that the MC68HC705C4A has less RAM and ROM, no ...
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Programmable Options These options are programmable in the mask option registers: • • These options are programmable in the option register (shown in Figure • • Address: Read: Write: Reset: SEC — Security Bit This bit is implemented as ...
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General Description IRQ — Interrupt Request Pin Sensitivity Bit IRQ is set only by reset, but can be cleared by software. This bit can be written only once. Bits 7–4 and 0 — Not used; always read 0 Bit 2 ...
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EPROM PROGRAMMING V CONTROL PP EPROM/OTPROM — 4144 BYTES RESET CPU CONTROL IRQ CPU REGISTERS 0 CONDITION CODE REGISTER OSC2 OSCILLATOR OSC1 COP WATCHDOG V DD POWER Port B pins also function as external interrupts. † PC7 ...
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General Description Technical Data RESET 2 39 IRQ PA7 5 36 PA6 6 35 PA5 7 34 PA4 8 33 PA3 32 9 PA2 PA1 10 31 PA0 11 30 PB0 ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA PA5 7 PA4 8 9 PA3 PA2 10 11 PA1 PA0 12 PB0 13 14 PB1 PB2 15 PB3 16 PB4 17 Figure 1-4. 44-Lead PLCC Pin Assignments ...
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General Description Technical Data RESET 2 41 IRQ PA7 4 39 PA6 5 38 PA5 6 37 PA4 7 36 PA3 8 35 PA2 9 34 PA1 10 33 PA0 11 32 PB0 ...
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Pin Functions The following paragraphs describe the MC68HC705C4A signals. 1.7.1 V and from a single power supply. Very fast signal transitions occur on the MCU pins, placing high short-duration current demands on the power ...
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General Description 1.7.2.1 Crystal Resonator The circuit in parallel resonant crystal. Follow the crystal supplier’s recommendations, because the crystal parameters determine the external component values required to provide reliable startup and maximum stability. The load capacitance values used in the ...
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To minimize output distortion, mount the resonator and capacitors as close as possible to the pins. NOTE: The bus frequency (f (f OSC period. MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA OSC1 RESONATOR C Figure 1-9. 2-Pin ...
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General Description 1.7.2.3 External Clock Signal An external clock from another CMOS-compatible device can drive the OSC1 input, with the OSC2 pin unconnected, as NOTE: The bus frequency (f the processor clock cycle is two times the f 1.7.3 External ...
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Output Compare Pin (TCMP) The TCMP pin is the output compare pin for the on-chip capture/compare timer. See 1.7.7 Port A I/O Pins (PA7–PA0) These eight I/O lines comprise port A, a general-purpose, bidirectional I/O port. The pins are ...
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General Description Technical Data 34 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 General Description MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.2 Introduction This section describes the organization of the on-chip memory. 2.3 Memory Map The central processor unit (CPU) can address eight Kbytes of memory and ...
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Memory subroutine call to save the CPU state. The stack pointer decrements during pushes and increments during pulls. Figure 2-1 shown in registers. Additional I/O registers have these addresses: • • • 2.4 Input/Output (I/O) The first 32 addresses of ...
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EPROM/OTPROM (PROM) An MCU with a quartz window has a maximum of 4144 bytes of EPROM. The quartz window allows the EPROM erasure with ultraviolet light MCU without a quartz window, the EPROM cannot be erased and ...
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Memory $0000 I/O REGISTERS 32 BYTES $001F $0020 $002F $0030 USER PROM 48 BYTES $004F $0050 RAM 176 BYTES $00BF ...
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Addr. Register Name Port A Data Register $0000 (PORTA) See page 74. Port B Data Register $0001 (PORTB) See page 77. Port C Data Register $0002 (PORTC) See page 81. Port D Fixed Input Register $0003 (PORTD) See page 84. ...
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Memory Addr. Register Name SPI Control Register $000A (SPCR) See page 143. SPI Status Register $000B (SPSR) See page 145. SPI Data Register $000C (SPDR) See page 143. Baud Rate Register $000D (Baud) See page 130. SCI Control Register 1 ...
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Addr. Register Name Timer Status Register $0013 (TSR) See page 92. Input Capture Register $0014 High (ICRH) See page 96. Input Capture Register $0015 Low (ICRL) See page 96. Output Compare Register High (OCRH) $0016 See page 96. Output Compare ...
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Memory Addr. Register Name EPROM Programming $001C Register (PROG) See page 105. $001D Unimplemented $001E Unimplemented $001F Unimplemented Option Register $1FDF (Option) See page 112. * Implemented as an EPROM cell Mask Option Register 1 $1FF0 (MOR1) See page 113. ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 3.1 Contents 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 3.2 Introduction This section describes the central processor unit (CPU) registers. MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Section 3. Central Processor Unit (CPU) ...
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Central Processor Unit (CPU) 3.3 CPU Registers Figure 3-1 • • • • • These are hard-wired registers within the CPU and are not part of the memory map. Bit Bit 12 11 Technical Data 44 shows ...
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Accumulator The accumulator (A) shown in register. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. Read: Write: Reset: 3.3.2 Index Register In the indexed addressing modes, the CPU uses the byte in ...
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Central Processor Unit (CPU) 3.3.3 Stack Pointer The stack pointer (SP) shown in contains the address of the next free location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer initializes to ...
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Program Counter The program counter (PC) shown in contains the address of the next instruction or operand to be fetched. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction ...
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Central Processor Unit (CPU) 3.3.5 Condition Code Register The condition code register (CCR) shown in register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four bits that indicate the ...
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N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result (bit 7 in the results is a logic 1). Reset has no effect on the negative flag. ...
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Central Processor Unit (CPU) Technical Data 50 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 Central Processor Unit (CPU) MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.4 4.2 Introduction This section describes how interrupts temporarily change the normal processing sequence. MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Introduction . . ...
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Interrupts 4.3 Interrupt Sources These sources can generate interrupts: • • • • • • The IRQ pin, port B pins, timer, SCI, and SPI can be masked (disabled) by setting the I bit of the condition code register (CCR). ...
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External Interrupt (IRQ) An interrupt signal on the IRQ pin latches an external interrupt request. After completing the current instruction, the CPU tests these bits: • • Setting the I bit in the condition code register disables external interrupts. ...
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Interrupts EDGE- AND LEVEL-SENSITIVE TRIGGER OPTION REGISTER V DD INTERRUPT PIN Figure 4-1. External Interrupt Internal Function Diagram IRQ PIN a. Edge-Sensitive Trigger Condition. The minimum pulse width (t or 250 MHz). The period t OP ...
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The IRQ pin is negative edge-triggered only or negative edge- and low level-triggered, depending on the external interrupt triggering mask option selected. When the edge- and level-triggering mask option is selected: • • When the edge-triggering mask option is selected: ...
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Interrupts Port B external interrupt pins can be falling-edge sensitive only or both falling-edge and low-level sensitive, depending on the state of the IRQ bit in the option register at location $1FDF. When the IRQ bit is a logic 1, ...
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READ $0005 WRITE $0005 RESET WRITE $0001 READ $0001 FROM OPTION REGISTER FROM OTHER PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA PBPU7 FROM MOR1 DATA DIRECTION REGISTER B BIT DDRB7 PORT ...
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Interrupts • 4.3.5 SCI Interrupts The SCI can generate these interrupts: • • • • • Setting the I bit in the condition code register disables all SCI interrupts. • • • Technical Data 58 Timer Overflow Interrupt — The ...
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SPI Interrupts The SPI can generate these interrupts: • • Setting the I bit in the condition code register disables all SPI interrupts. • • MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA SCI Receiver Overrun Interrupt — ...
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Interrupts 4.4 Interrupt Processing The CPU takes these actions to begin servicing an interrupt: 1. Stores the CPU registers on the stack in the order shown 2. Sets the I bit in the condition code register to prevent further 3. ...
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The return-from-interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in STACKING NOTE: If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A ...
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Interrupts FROM RESET I BIT IN YES CCR REGISTER SET? EXTERNAL IRQ INTERRUPT? TIMER INTERRUPT? SCI INTERRUPT? SPI INTERRUPT? FETCH NEXT INSTRUCTION SWI INSTRUCTION? RTI INSTRUCTION? Figure 4-5. Reset and Interrupt Processing Flowchart Technical Data 62 NO YES CLEAR IRQ ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 5.1 Contents 5.2 5.3 5.3.1 5.3.2 5.3.3 5.2 Introduction This section describes how resets initialize the MCU. 5.3 Reset Sources A reset immediately stops the operation of the instruction being executed, initializes certain control ...
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Resets 5.3.1 Power-On Reset (POR) A positive transition on the V The POR is strictly for the power-up condition and cannot be used to detect drops in power supply voltage. A 4064 t active allows the clock generator to stabilize. ...
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Two memory locations control operation of the COP watchdog: • • Figure 5-1 COP WATCHDOG (MC68HC05C4A TYPE) COPC INTERNAL CLOCK MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA COP Enable Bit (NCOPE) in Mask ...
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Resets Technical Data 66 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 Resets MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 6.1 Contents 6.2 6.3 6.3.1 6.3.2 6.3.3 6.4 6.5 6.2 Introduction This section describes the three low-power modes: • • • 6.3 Stop Mode The STOP instruction places the microcontroller unit (MCU) in its ...
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Low-Power Modes STOP OSCILLATOR AND ALL CLOCKS CLEAR I BIT NO RESET EXTERNAL INTERRUPT (IRQ) NO YES TURN ON OSCILLATOR WAIT FOR TIME DELAY TO STABILIZE 1. FETCH RESET VECTOR 2. SERVICE INTERRUPT: a. STACK b. SET I BIT c. ...
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SCI During Stop Mode When the MCU enters stop mode, the baud rate generator stops, halting all SCI activity. If the STOP instruction is executed during a transmitter transfer, that transfer is halted low input to the ...
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Low-Power Modes 6.3.3 COP Watchdog in Stop Mode The STOP instruction has these effects on the computer operating properly (COP) watchdog: • • If the RESET pin brings the MCU out of stop mode, the COP watchdog begins counting immediately. ...
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Figure 6-2. COP Watchdog in Stop Mode Flowchart (NCOPE = 1) MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA STOP CLEAR I BIT IN CCR CLEAR COP COUNTER TURN OFF INTERNAL OSCILLATOR TURN OFF COP COUNTER YES EXTERNAL RESET ...
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Low-Power Modes 6.5 Data-Retention Mode In data-retention mode, the MCU retains random-access memory (RAM) contents and central processor unit (CPU) register contents at V voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 7.1 Contents 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 7.6 7.2 Introduction This section describes the programming of ports and D. MC68HC705C4A • MC68HSC705C4A — ...
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Parallel Input/Output (I/O) 7.3 Port A Port 8-bit, general-purpose, bidirectional input/output (I/O) port. 7.3.1 Port A Data Register The port A data register (PORTA) shown in latch for each of the eight port A pins. When a ...
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Data Direction Register A The contents of data direction register A (DDRA) shown in determine whether each port A pin is an input or an output. Writing a logic DDRA bit enables the output buffer for ...
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Parallel Input/Output (I/O) 7.3.3 Port A Logic Figure 7-3 When a port A pin is programmed output, the state of its data register bit determines the state of the output pin. When a port A pin is ...
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Port B Port 8-bit, general-purpose, bidirectional I/O port. Port B pins can also be configured to function as external interrupts. The port B pullup devices are enabled in mask option register 1 (MOR1). See Option Register ...
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Parallel Input/Output (I/O) 7.4.2 Data Direction Register B The contents of data direction register B (DDRB) shown in determine whether each port B pin is an input or an output. Writing a logic DDRB bit enables the ...
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Port B Logic Figure 7-6 READ $0005 WRITE $0005 RESET WRITE $0001 READ $0001 FROM OPTION REGISTER FROM OTHER PORT B PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA shows the port B ...
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Parallel Input/Output (I/O) When a port B pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin itself. When a port B pin is programmed as ...
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Port C Port 8-bit, general-purpose, bidirectional I/O port. PC7 has a high current sink and source capability. 7.5.1 Port C Data Register The port C data register (PORTC) shown in latch for each of the eight ...
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Parallel Input/Output (I/O) 7.5.2 Data Direction Register C The contents of data direction register C (DDRC) shown in determine whether each port C pin is an input or an output. Writing a logic DDRC bit enables the ...
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Port C Logic Figure 7-9 When a port C pin is programmed as an output, reading the port bit reads the value of the data latch and not the voltage on the pin. When a port C pin is ...
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Parallel Input/Output (I/O) 7.6 Port D Port 7-bit, special-purpose, input-only port that has no data register. Reading address $0003 returns the logic states of the port D pins. Port D shares pins PD5–PD2 with the serial peripheral ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 8.1 Contents 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.2 Introduction This section describes the operation of the 16-bit capture/compare timer. Figure 8-1 summary of the timer input/output (I/O) registers. ...
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Capture/Compare Timer EDGE SELECT/ TCAP DETECT LOGIC $0012 TIMER CONTROL REGISTER Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers. Because the counter is 16 bits long ...
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Addr. Register Name Timer Control Register $0012 (TCR) See page 90. Timer Status Register $0013 (TSR) See page 92. Input Capture Register $0014 High (ICRH) See page 96. Input Capture Register $0015 Low (ICRL) See page 96. Output Compare Register ...
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Capture/Compare Timer 8.3.1 Input Capture The input capture function can record the time at which an external event occurs. When the input capture circuitry detects an active edge on the input capture pin (TCAP), it latches the contents of the ...
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Output Compare The output compare function can generate an output signal when the 16-bit counter reaches a selected value. Software writes the selected value into the output compare registers. On every fourth internal clock cycle the output compare circuitry ...
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Capture/Compare Timer 8.4 Timer I/O Registers These registers control and monitor the timer operation: • • • • • • 8.4.1 Timer Control Register The timer control register as shown in functions: • • • • • Address: Read: Write: ...
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ICIE — Input Capture Interrupt Enable Bit This read/write bit enables interrupts caused by an active signal on the TCAP pin. Reset clears the ICIE bit. OCIE — Output Compare Interrupt Enable Bit This read/write bit enables interrupts caused by ...
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Capture/Compare Timer 8.4.2 Timer Status Register This read-only register shown in events: • • • Address: Read: Write: Reset: ICF — Input Capture Flag The ICF bit is set automatically when an edge of the selected polarity occurs on the ...
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TOF — Timer Overflow Flag The TOF bit is set automatically when the 16-bit counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with TOF set and then reading the low byte ...
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Capture/Compare Timer NOTE: To prevent interrupts from occurring between readings of TRH and TRL, set the interrupt mask (I bit) in the condition code register before reading TRH, and clear the mask after reading TRL. 8.4.4 Alternate Timer Registers The ...
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Reading ATRH returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer, as shown in Figure NOTE: To prevent interrupts from occurring between readings of ATRH and ATRL, ...
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Capture/Compare Timer Register Name and Address: Input Capture Register High — $0014 Read: Write: Reset: Register Name and Address: Input Capture Register Low — $0015 Read: Write: Reset: 8.4.6 Output Compare Registers When the value of the 16-bit counter matches ...
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To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use this procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to ...
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Capture/Compare Timer Technical Data 98 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 Capture/Compare Timer MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 9.1 Contents 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.5 9.5.1 9.5.2 9.5.3 9.6 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Section 9. EPROM/OTPROM (PROM) Introduction . . ...
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EPROM/OTPROM (PROM) 9.2 Introduction This section describes erasable, programmable read-only memory/one-time programmable read-only memory (EPROM/OTPROM (PROM)) programming. 9.3 EPROM/OTPROM (PROM) Programming The internal PROM can be programmed efficiently using the Motorola MC68HC05PGMR-2 programmer board, which can be purchased from a ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA START AT BEGINNING WRITE PROM DATA YES NTRYS = NTRYS + 1 NO Figure 9-1. EPROM/OTPROM Programming Flowchart EPROM/OTPROM (PROM) EPROM/OTPROM (PROM) EPROM/OTPROM (PROM) Programming START APPLY V PP NTRYS = 0 OF ...
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EPROM/OTPROM (PROM + – GND 1 P3 RXD 3 TXD 2 CTS 5 DSR 6 DCD 8 DTR 20 GND 1 GND 7 Notes: 1. The asterisk (*) denotes ...
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2.0 MHz R10* 470 VERF DS2* (VERF) M (PROG) N PROG DS1* (A5) (A4) (A3) R11* (A2) 470 (A1) ...
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EPROM/OTPROM (PROM) To program the PROM MCU, the MCU is installed in the PCB, along with an EPROM device programmed with user code; the MCU is then subjected to a series of routines. The routines necessary to program, verify, and ...
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Program Register The program register shown in programming. Address: Read: Write: Reset: LAT — Latch Enable Bit This bit is both readable and writable. PGM — Program Bit If LAT is cleared, PGM cannot be set. Bits 1 and ...
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EPROM/OTPROM (PROM) 9.3.2 Preprogramming Steps Before programming the PROM using an MC68HC05PGMR PCB in standalone mode, the user should ensure that: • • • • • CAUTION: If the V MCU device will suffer permanent damage. Once those conditions are ...
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PROM Programming Routines The routines described in this subsection are necessary to program, verify, and secure the PROM device and other routines available to the user. 9.4.1 Program and Verify PROM The program and verify PROM routine copies the ...
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EPROM/OTPROM (PROM) 9.4.2 Verify PROM Contents The verify PROM contents routine is normally run automatically after the PROM is programmed. Direct entry to this routine causes the PROM contents of the MCU to be compared to the contents of the ...
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Secure PROM and Verify This routine is used after the PROM is programmed successfully to verify the contents of the MCU PROM against the contents of the EPROM and then to secure the PROM. To accomplish this routine, take ...
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EPROM/OTPROM (PROM) No LED is illuminated during this routine. Further, the end of the routine does not mean that the SEC bit was verified. To ensure that security is properly enabled, attempt to perform another verify routine. If the green ...
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Execute Program in RAM This routine allows the MCU to transfer control to a program previously loaded in RAM. This program is executed once bootstrap mode is entered, if switch the ON position and switch 2 ...
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EPROM/OTPROM (PROM) 9.5 Control Registers This subsection describes three registers that control: • • • • • 9.5.1 Option Register The option register (option) shown in IRQ sensitivity, enable the PROM security, and select the memory configuration. Address: Read: Write: ...
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IRQ — Interrupt Request Pin Sensitivity Bit IRQ is set only by reset, but can be cleared by software. This bit can only be written once. Bits 7–4 and 0 — Not used; always read 0 Bit 2 — Unaffected ...
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EPROM/OTPROM (PROM) 9.5.3 Mask Option Register 2 The mask option register 2 (MOR2) shown in register that enables the non-programmable COP watchdog. Data from MOR2 is latched on the rising edge of the voltage on the RESET pin. (See Reset.) ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A Section 10. Serial Communications Interface (SCI) 10.1 Contents 10.2 10.3 10.4 10.5 10.5.1 10.5.2 10.6 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.2 Introduction The serial communications interface (SCI) module allows high-speed asynchronous communication with peripheral ...
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Serial Communications Interface (SCI) 10.3 Features Features of the SCI module include: • • • • • • • • • 10.4 SCI Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT 0 BIT ...
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SCI Operation The SCI allows full-duplex, asynchronous, RS232 or RS422 serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud-rate generator. Operation of ...
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Serial Communications Interface (SCI) 1X BAUD RATE CLOCK SCCR1 ($000E) SCI RECEIVE REQUESTS SCI INTERRUPT REQUEST Technical Data 118 SCDR ($0011) TRANSMIT SHIFT REGISTER TRANSMITTER CONTROL LOGIC SCSR ($0010) ...
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Addr. Register Name Baud Rate Register $000D (Baud) See page 130. SCI Control Register 1 $000E (SCCR1) See page 124. SCI Control Register 2 $000F (SCCR2) See page 125. SCI Status Register $0010 (SCSR) See page 128. SCI Data Register ...
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Serial Communications Interface (SCI) • • 10.5.2 Receiver Figure 10-4 Figure 10-3 • Technical Data 120 Idle Characters — An idle character contains all logic 1s and has no start or stop bits. Idle character length depends on the M ...
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BAUD RATE CLOCK PD0/ PIN BUFFER RDI AND CONTROL M SCCR1 ($000E) SCI TRANSMIT REQUESTS SCI INTERRUPT REQUEST • MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA 16 DATA RECOVERY DISABLE DRIVER RE SCSR ($0010) RDRF RIE IDLE ILIE OR ...
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Serial Communications Interface (SCI) • • • • Technical Data 122 After a complete character shifts into the receive shift register, the data portion of the character is transferred to the SCDR, setting the receive data register full (RDRF) flag. ...
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SCI I/O Registers These I/O registers control and monitor SCI operation: • • • • 10.6.1 SCI Data Register (SCDR) The SCI data register (SCDR) shown in characters received and for characters transmitted. Address: Read: Write: Reset: MC68HC705C4A • ...
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Serial Communications Interface (SCI) 10.6.2 SCI Control Register 1 SCI control register 1 (SCCR1) shown in functions: • • • Address: Read: Write: Reset: R8 — Bit 8 (Received) When the SCI is receiving 9-bit characters the ninth ...
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WAKE — Wakeup Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition of the PD0/RDI pin. Reset has no ...
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Serial Communications Interface (SCI) TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables SCI interrupt requests when the TC bit becomes set. Reset clears the TCIE bit. RIE — Receive Interrupt Enable Bit This read/write bit enables SCI ...
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RWU — Receiver Wakeup Enable Bit This read/write bit puts the receiver in a standby state. Typically, data transmitted to the receiver clears the RWU bit and returns the receiver to normal operation. The WAKE bit in SCCR1 determines whether ...
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Serial Communications Interface (SCI) Address: Read: Write: Reset: TDRE — Transmit Data Register Empty Bit This clearable, read-only bit is set when the data in the SCDR transfers to the transmit shift register. TDRE generates an interrupt request if the ...
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IDLE — Receiver Idle Bit This clearable, read-only bit is set when consecutive logic 1s appear on the receiver input. IDLE generates an interrupt request if the ILIE bit in SCCR2 is also set. Clear the IDLE ...
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Serial Communications Interface (SCI) 10.6.5 Baud Rate Register (Baud) The baud rate register (baud) shown in rate for both the receiver and the transmitter. Address: Read: Write: Reset: SCP1 and SCP0 — SCI Prescaler Select Bits These read/write bits control ...
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SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate, as shown in Table Table 10-3 frequencies of 2 MHz, 4 MHz, and 4.194304 MHz. MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA 10-2. Reset has ...
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Serial Communications Interface (SCI) SCP[1: Technical Data 132 ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A Section 11. Serial Peripheral Interface (SPI) 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.2 11.5 11.6 11.7 11.7.1 11.7.2 11.7.3 11.8 11.9 11.9.1 11.9.2 11.9.3 11.2 Introduction The serial peripheral interface (SPI) module allows full-duplex, ...
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Serial Peripheral Interface (SPI) 11.3 Features Features of the SPI include: • • • • • • • • Figure 11-1 summary of the SPI input/output (I/O) registers. Technical Data 134 Full-duplex operation Master and slave modes Four programmable master ...
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INTERNAL CLOCK (XTAL 2) DIVIDER SELECT SPI CONTROL SPSR ($000B) SPI INTERRUPT MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA SPI SHIFT REGISTER SPDR ($000C) SPI CLOCK (MASTER) MSTR ...
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Serial Peripheral Interface (SPI) Addr. Register Name SPI Control Register $000A (SPCR) See page 143. SPI Status Register $000B (SPSR) See page 145. SPI Data Register $000C (SPDR) See page 143. Figure 11-2. SPI I/O Register Summary 11.4 Operation The ...
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In a slave SPI, data enters the shift register under the control of the serial clock from the master SPI. After a byte enters the shift register of a slave SPI, it transfers to the SPDR. To prevent an overrun ...
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Serial Peripheral Interface (SPI) 11.4.2 Pin Functions in Slave Mode Clearing the MSTR bit in the SPCR configures the SPI for operation in slave mode. The slave-mode functions of the SPI pins are: • • • • When CPHA = ...
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Example: LDA #$1C STA SPCR LDA #$4C STA SPCR 11.5 Multiple-SPI Systems In a multiple-SPI system, all PD4/SCK pins are connected together, all PD3/MOSI pins are connected together, and all PD2/MISO pins are connected together. Before a transmission, one SPI ...
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Serial Peripheral Interface (SPI) Figure 11-5. Two Master/Slaves and Three Slaves Block Diagram 11.6 Serial Clock Polarity and Phase To accommodate the different serial communication requirements of peripheral devices, software can change the phase and polarity of the SPI serial ...
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SPI Error Conditions These conditions produce SPI system errors: • • • 11.7.1 Mode Fault Error A mode fault error results when a logic 0 occurs on the PD5/SS pin of a master SPI. The MCU takes these actions ...
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Serial Peripheral Interface (SPI) 11.7.3 Overrun Error Failing to read the byte in the SPDR before a subsequent byte enters the shift register causes an overrun condition overrun condition, all incoming data is lost until software clears SPIF. ...
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SPI Data Register The SPDR shown in received by the SPI. Writing a byte to the SPDR places the byte directly into the SPI shift register. Address: Read: Write: Reset: 11.9.2 SPI Control Register The SPCR shown in • ...
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Serial Peripheral Interface (SPI) SPI — SPI Enable Bit This read/write bit enables the SPI. Reset clears the SPE bit. MSTR — Master Bit This read/write bit selects master mode operation or slave mode operation. Reset clears the MSTR bit. ...
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SPI Status Register The SPSR shown in conditions: • • • Address: Read: Write: Reset: SPIF — SPI Flag This clearable, read-only bit is set each time a byte shifts out of or into the shift register. SPIF generates ...
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Serial Peripheral Interface (SPI) MODF — Mode Fault Bit This clearable, read-only bit is set when a logic 0 occurs on the PD5/SS pin while the MSTR bit is set. MODF generates an interrupt request if the SPIE bit is ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 12.1 Contents 12.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.3.6 12.3.7 12.3.8 12.4 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.5 12.6 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Section 12. Instruction Set Introduction . . ...
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Instruction Set 12.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication ...
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Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator ...
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Instruction Set 12.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the ...
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Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch ...
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Instruction Set 12.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Technical ...
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Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC705C4A • ...
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Instruction Set 12.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Table 12-3. Jump and Branch Instructions Instruction Branch if carry bit clear Branch if carry bit set Branch if equal Branch if half-carry bit clear Branch if half-carry bit set Branch if higher ...
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Instruction Set 12.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the ...
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Control Instructions These instructions act on CPU registers and control CPU operation during program execution. MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA Table 12-5. Control Instructions Instruction Clear carry bit Clear interrupt mask No operation Reset stack pointer Return ...
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Instruction Set 12.5 Instruction Set Summary Table 12-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add ...
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Table 12-6. Instruction Set Summary (Sheet Source Operation Form BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X ...
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Instruction Set Table 12-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ...
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Table 12-6. Instruction Set Summary (Sheet Source Operation Form JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X ...
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Instruction Set Table 12-6. Instruction Set Summary (Sheet Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine ...
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Table 12-6. Instruction Set Summary (Sheet Source Operation Form TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications 13.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply ...
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... Plastic shrink DIP (SDIP) TEST POINT C (SEE TABLE) MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA (1) Rating (2) MC68HC705C4ACB MC68HC705C4ACFB MC68HC705C4ACP MC68HC705C4ACFN Plastic dual in-line package (PDIP Plastic shrink dual in-line package (SDIP Plastic-leaded chip carrier (PLCC Quad flat pack (QFP) Characteristic PA7–PA0 R2 PB7– ...
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Electrical Specifications 13.6 Power Considerations The average chip junction temperature, T Where For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. ...
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DC Electrical Characteristics Characteristic Output voltage, I 10.0 A Load Output high voltage I = –0.8 mA, PA7–PA0, PB7–PB0, PC6–PC0, TCMP Load (see Figure 13- –1.6 mA, PD4–PD1 (see Load I = –5.0 mA, PC7 Load ...
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Electrical Specifications 13.8 3.3-Volt DC Electrical Characteristics Characteristic Output voltage, I 10.0 A Load Output high voltage I = –0.2 mA Load PA7–PA0, PB7–PB0, PC6–PC0, TCMP (see Figure 13- –0.4 mA Load PD4–PD1 (see Figure 13- ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA 5.0 4.0 3.0 2.0 1.0 0.8 SEE NOTE 2 0 0.2 V – Notes 5.0 V, devices are specified and tested for (V DD 800 ...
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Electrical Specifications Figure 13-2. Typical Voltage Compared to Current (Continued) Technical Data 172 6.0 5.0 4.0 3.0 2.0 1.6 1.0 SEE NOTE 2 0 0.1 0.2 V (VOLTS) OL Notes 5.0 V, devices are ...
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MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MOTOROLA 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 INTERNAL FREQUENCY 1 t (a) Wait Mode 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 ...
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Electrical Specifications Technical Data 174 3 – 3.3 V 10% DD 2.5 mA 2.0 mA 1.5 mA 1.0 mA 500 250 kHz 500 kHz INTERNAL CLOCK FREQUENCY (XTAL ...
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Control Timing Characteristic Frequency of operation Crystal option External clock option Internal operating frequency Crystal (f 2) OSC External clock (f 2) OSC Cycle time (see Figure 13-7) Crystal oscillator startup time (see Stop recovery startup time (crystal ...
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Electrical Specifications 13.10 3.3-Volt Control Timing Characteristic Frequency of operation Crystal option External clock option Internal operating frequency Crystal (f 2) OSC External clock (f 2) OSC Cycle time (see Figure 13-7) Crystal oscillator startup time (see Stop recovery startup ...
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...
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VDDR V V THRESHOLD (1-2 V TYPICAL ...
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Serial Peripheral Interface (SPI) Timing (1) Number Operating frequency Master Slave Cycle time Master 1 Slave Enable lead time Master 2 Slave Enable lag time Master 3 Slave Clock (SCK) high time Master 4 Slave Clock (SCK) low ...
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Electrical Specifications (1) Number Characteristic Data hold time (outputs) Master (after capture edge) 11 Slave (after enable edge) (7) Rise time 12 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) (8) Fall time 13 SPI outputs (SCK, ...
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Serial Peripheral Interface (SPI) Timing (1) Number Operating frequency Master Slave Cycle time Master 1 Slave Enable lead time Master 2 Slave Enable lag time Master 3 Slave Clock (SCK) high time Master 4 Slave Clock (SCK) low ...
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Electrical Specifications (1) Number Characteristic Data hold time (outputs) Master (after capture edge) 11 Slave (after enable edge) (7) Rise time 12 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) (8) Fall time 13 SPI outputs (SCK, ...
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SS SS pin of master held high. INPUT SCK (CPOL = 0) NOTE OUTPUT SCK (CPOL = 1) NOTE OUTPUT MISO INPUT 10 MOSI OUTPUT 13 Note: This first clock edge is generated internally, but is not seen at the ...
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Electrical Specifications SS INPUT SCK (CPOL = 0) (INPUT 2 SCK (CPOL = 1) INPUT 8 MISO SLAVE INPUT 6 MOSI MSB IN OUTPUT Note: Not defined, but normally MSB of character just received SS INPUT SCK (CPOL = 0) ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A 14.1 Contents 14.2 14.3 14.4 14.5 14.6 14.2 Introduction Package dimensions available at the time of this publication for the MC68HC705C4A are provided in this section. The packages are: • • • • MC68HC705C4A ...
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Mechanical Specifications 14.3 40-Pin Plastic Dual In-Line Package (PDIP ...
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Plastic-Leaded Chip Carrier (PLCC) -N- - ...
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Mechanical Specifications 14.6 44-Pin Quad Flat Pack (QFP - -D- 0.20 (0.008) M 0.05 (0.002) A-B 0.20 (0.008 -C- H SEATING G PLANE DATUM -H- PLANE DETAIL C Figure 14-4. MC68HC705C4AFB Package ...
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... Table 15-1. MC68HC705C4A Order Numbers Package Type package (PDIP) package (SDIP) chip carrier (PLCC) pack (QFP) Ordering Information Temperature Order Number Range – +85 C MC68HC705C4AC – +85 C MC68HC705C4ACB – +85 C MC68HC705C4ACFN – +85 C MC68HC705C4ACFB (1) (2) P (3) (4) (5) Technical Data 189 ...
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Ordering Information Technical Data 190 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 Ordering Information MOTOROLA ...
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Technical Data — MC68HC705C4A • MC68HSC705C4A A.1 Contents A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9 A.2 Introduction The MC68HSC705C4A is an enhanced, high-speed version of the MC68HC705C4A, featuring a 4-MHz bus speed. The data in this document applies to ...
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MC68HSC705C4A A.3 5.0-Volt High-Speed DC Electrical Characteristics Characteristic Output high voltage I = –0.8 mA Load PA7–PA0, PB7–PB0, PC6–PC0, TCMP I = –1.6 mA Load PD4–PD1 I –5.0 mA Load PC7 Output low voltage I = 1.6 mA Load PA7–PA0, ...
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A.4 3.3-Volt High-Speed DC Electrical Characteristics Characteristic Output high voltage I = –0.2 mA Load PA7–PA0, PB7–PB0, PC6–PC0, TCMP I = –0.4 mA Load PD4–PD1 I = –1.5 mA Load PC7 Output low voltage I = 0.4 mA Load PA7–PA0, ...
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MC68HSC705C4A A.5 5.0-Volt High-Speed Control Timing Characteristic Oscillator frequency Crystal oscillator External clock Internal operating frequency (f OSC Crystal oscillator External clock Cycle time Input capture pulse width Interrupt pulse width low (edge-triggered) OSC1 pulse width ...
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A.7 5.0-Volt High-Speed SPI Timing Diagram Characteristic (1) Number Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time 2 Master Slave Enable lag time 3 Master Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low ...
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MC68HSC705C4A Diagram Characteristic (1) Number Data hold time (outputs) 11 Master (after capture edge) Slave (after enable edge) (7) Rise time 12 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) (8) Fall time 13 SPI outputs (SCK, ...
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A.8 3.3-Volt High-Speed SPI Timing Diagram (1) Number Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time 2 Master Slave Enable lag time 3 Master Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low time ...
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MC68HSC705C4A Diagram (1) Number Data hold time (outputs) 11 Master (after capture edge) Slave (after enable edge) (7) Rise time 12 SPI outputs (SCK, MOSI, MISO) SPI inputs (SCK, MOSI, MISO, SS) (8) Fall time 13 SPI outputs (SCK, MOSI, ...
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A.9 Ordering Information Table A-1 40-pin plastic dual in-line 44-lead plastic-leaded chip 44-pin quad flat pack (QFP) 42-pin shrink dual in-line Extended temperature range (– + Plastic dual in-line package (PDIP) ...
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MC68HSC705C4A Technical Data 200 MC68HC705C4A • MC68HSC705C4A — Rev. 3.0 MC68HSC705C4A MOTOROLA ...