mc68hc705c4acfn Freescale Semiconductor, Inc, mc68hc705c4acfn Datasheet - Page 76

• Manufacturer Part Number: mc68hc705c4acfn
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Parallel Input/Output (I/O)
7.3.3 Port A Logic
Technical Data
76
NOTE:
Figure 7-3
When a port A pin is programmed to be an output, the state of its data
register bit determines the state of the output pin. When a port A pin is
programmed to be an input, reading the port A data register returns the
logic state of the pin.
The data latch can always be written, regardless of the state of its DDRA
bit.
To avoid excessive current draw, tie all unused input pins to V
or change I/O pins to outputs by writing to DDRA in user code as early
as possible.
1. Hi-Z = high impedance
2. Writing affects data register but does not affect input.
DDRA Bit
Table 7-1
0
1
READ $0004
WRITE $0004
WRITE $0000
READ $0000
is a diagram of the port A I/O logic.
Parallel Input/Output (I/O)
I/O Pin Mode
Input, Hi-Z
summarizes the operation of the port A pins.
RESET
Output
Table 7-1. Port A Pin Functions
Figure 7-3. Port A I/O Logic
(1)
DATA DIRECTION
PORT A DATA
REGISTER A
REGISTER
BIT DDRAx
BIT PAx
Accesses to DDRA
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
DDRA7–DDRA0
DDRA7–DDRA0
Read/Write
PA7–PA0
Accesses to PORTA
Read
Pin
PA7–PA0
MOTOROLA
PA7–PA0
DD
Write
PAx
or V
(2)
SS