mc68hc705c4acfn Freescale Semiconductor, Inc, mc68hc705c4acfn Datasheet - Page 95

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mc68hc705c4acfn

Manufacturer Part Number
mc68hc705c4acfn
Description
M68hc05 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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8.4.5 Input Capture Registers
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
MOTOROLA
NOTE:
NOTE:
Reading ATRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer, as shown in
Figure
To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt mask (I bit) in the condition code register before
reading ATRH, and clear the mask after reading ATRL.
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers shown in
inhibits further captures until ICRL is read. Reading ICRL after reading
the timer status register clears the input capture flag (ICF). Writing to the
input capture registers has no effect.
To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt mask (I bit) in the condition code register before
reading ICRH and clear the mask after reading ICRL.
$001A
8-10.
15
ALTERNATE TIMER REGISTER HIGH
Figure 8-10. Alternate Timer Register Reads
Capture/Compare Timer
Figure
READ ATRH
8-11. Reading ICRH before reading ICRL
INTERNAL DATA BUS
LATCH
8
7
7
ALTERNATE TIMER REGISTER LOW
LOW BYTE BUFFER
Capture/Compare Timer
Timer I/O Registers
Technical Data
0
0
$001B
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