mc68hc705c4acfn Freescale Semiconductor, Inc, mc68hc705c4acfn Datasheet - Page 64

• Manufacturer Part Number: mc68hc705c4acfn
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Resets
5.3.1 Power-On Reset (POR)
5.3.2 External Reset
5.3.3 Computer Operating Properly (COP) Watchdog Reset
Technical Data
64
NOTE:
A positive transition on the V
The POR is strictly for the power-up condition and cannot be used to
detect drops in power supply voltage.
A 4064 t
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 t
until the signal on the RESET pin goes to logic 1.
The minimum time required for the MCU to recognize a reset is 1 1/2
t
A timeout of the 18-stage ripple counter in the computer operating
properly (COP) watchdog timer generates a reset. The COP watchdog
timer, once enabled, is part of a software error detection system and
must be cleared periodically to start a new timeout period. The timeout
period is 65.536 ms when f
function of the crystal frequency. The equation is:
A COP timeout does not pull the RESET pin low.
For information on the COP watchdog timer in low-power modes, refer
to
CYC
Section 6. Low-Power
. A Schmitt trigger senses the logic level at the RESET pin.
CYC
(internal clock cycle) delay after the oscillator becomes
Resets
Timeout period =
CYC
Modes.
OSC
DD
MC68HC705C4A • MC68HSC705C4A — Rev. 3.0
, the MCU remains in the reset condition
= 4 MHz. The timeout period is a direct
pin generates a power-on reset (POR).
262,144
f
OSC
MOTOROLA