mc68hc705c4acfn Freescale Semiconductor, Inc, mc68hc705c4acfn Datasheet - Page 164

• Manufacturer Part Number: mc68hc705c4acfn
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MSB
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
BRSET0
BRCLR0
BRSET1
BRCLR1
BRSET2
BRCLR2
BRSET3
BRCLR3
BRSET4
BRCLR4
BRSET5
BRCLR5
BRSET6
BRCLR6
BRSET7
BRCLR7
Bit Manipulation
DIR
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR0
BCLR1
BCLR2
BCLR3
BCLR4
BCLR5
BCLR6
BCLR7
BSET0
BSET1
BSET2
BSET3
BSET4
BSET5
BSET6
BSET7
DIR
1
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCS/BLO
Branch
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
BHCC
BHCS
REL
BMC
BMS
BRA
BRN
BLS
BCC
BNE
BEQ
BPL
BHI
BMI
BIH
BIL
2
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
ASL/LSL
COM
NEG
ROR
ASR
ROL
DEC
DIR
LSR
TST
CLR
INC
3
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
4
5
1
1
1
1
1
1
ASLA/LSLA
1
1
1
1
1
1
COMA
RORA
NEGA
ASRA
ROLA
DECA
CLRA
LSRA
INCA
TSTA
MUL
INH
4
Read-Modify-Write
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
11
3
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
ASLX/LSLX
1
1
1
1
1
1
COMX
NEGX
RORX
DECX
LSRX
ASRX
ROLX
TSTX
CLRX
INCX
INH
5
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
Table 12-7. Opcode Map
ASL/LSL
COM
ROR
NEG
ASR
ROL
DEC
CLR
LSR
INC
TST
IX1
6
LSB of Opcode in Hexadecimal
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
6
6
6
6
6
6
6
6
6
5
6
1
1
1
1
1
1
1
1
1
1
1
ASL/LSL
COM
NEG
ROR
DEC
LSR
ASR
ROL
TST
CLR
INC
IX
7
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
5
5
5
5
5
5
5
5
5
4
5
1
1
1
1
1
STOP
WAIT
INH
RTS
SWI
RTI
8
Control
INH
INH
INH
INH
INH
10
9
6
2
2
1
1
1
1
1
1
1
1
NOP
INH
TAX
CLC
SEC
RSP
TXA
CLI
SEI
9
INH
INH
INH
INH
INH
INH
INH
INH
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LSB
IMM
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
BSR
LDA
LDX
BIT
A
0
MSB
REL
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
2
2
2
2
2
2
2
2
2
2
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
BRSET0
CMP
EOR
ORA
SUB
SBC
CPX
AND
LDA
STA
ADC
ADD
JMP
JSR
LDX
STX
DIR
BIT
B
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Register/Memory
Number of Cycles
Opcode Mnemonic
Number of Bytes/Addressing Mode
EXT
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
STA
JMP
JSR
LDX
STX
BIT
C
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
MSB of Opcode in Hexadecimal
4
4
4
4
4
4
4
5
4
4
4
4
3
6
5
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
CMP
EOR
ORA
SUB
SBC
CPX
AND
LDA
ADC
ADD
JMP
JSR
LDX
STX
STA
IX2
BIT
D
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
5
5
5
5
5
5
5
6
5
5
5
5
4
7
5
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
LDA
STA
JMP
JSR
LDX
STX
IX1
BIT
E
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMP
SUB
SBC
CPX
AND
LDA
EOR
ADC
ORA
ADD
JMP
LDX
STX
STA
JSR
BIT
IX
F
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
MSB
A
B
C
D
0
1
2
3
4
5
6
7
8
9
E
F
LSB