pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 142

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pxb4219

Manufacturer Part Number
pxb4219
Description
Iwe8 Interworking Element For 8 E1/t1 Lines
Manufacturer
Infineon Technologies Corporation
Datasheet
For reading the Interrupt Queue refer to
Each interrupt queue entry identifies a particular statistics counter that has reached its
threshold value. The format of the interrupt queue entries is as follows:
iq_ne
6.2.4
Read/write Address 26000
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 16 × 32 bits: 2 timer sets x 8 timers
RMADR
MPADR
timer_nr[3]
timer_nr
[2:0]
Data Sheet
iq_ne
31
23
15
7
17 16 15 14 13 12 11 10 9
Timers
1
channel_nr[3:0]
interrupt queue not empty
0 =
1 =
Timer number
Selects the timer set
0 =
1 =
Timer number
Number of the associated timer
15 14 13 12 11 10
0
0
interrupt queue is empty, no further entries
interrupt queue is not empty, further entries can be read
Timer set 2 indicated on MPIR2
Timer set 1 indicated on MPIR1
not used
1
H
1
to 2601F
0
0
Not used
Not used
H
Chapter
9
0
142
8
0
4.6.3.
7
8
0
PXB4219 / PXB4220 / PXB4221
6
7
0
port_nr
[2:0]
counter_nr [3:0]
5
6
0
4
5
0
3
4
Memory Structure
timer_nr[3:0]
2
3
1
2
2002-05-06
channel_
nr[4]
0
1
24
16
8
0
0
0

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