pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 202

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

7.46
Read/Write Address 00103
Reset value: 0020
gim
ds1
parc
pdcri
srst
lptd
Data Sheet
ds1
15
7
Internal
(icrcconf)
parc
Generic interface mode
0 =
1 =
DS1 Mode
0 =
1 =
Parity Check
Inverts all parity bits in the ICRC. All enabled parity checkers will
generate interrupts
0 =
1 =
Power Down Clock Recovery Interface
0 =
1 =
Software Reset
The bit srts is set by the software, but reset by the ICRC. Reading this
bit will always give the Reset value: “0”.
0 =
1 =
Loop back clock recovery interface transmitted data downstream
H
FAM: 8.192 MHz is expected/generated.
GIM: 2.048 MHz (E1) or 1.544 MHz (T1) expected/generated.
E1: The receive clocks are divided to 2.048 MHz. Output clocks
are 8.192 MHz in case of FAM or 2.048 MHz in case of GIM.
T1: The receive clocks are divided to 1.544 MHz. Output clocks
are 8.192 MHz in case of FAM or 1.544 MHz in case of GIM.
Disabled
Enabled
Normal operation
The internal clock recovery interface is put in power down mode.
No data is received, no errors are generated and the parity check
is disabled.
Normal operation
Reset ICRC
Clock
pdcri
H
Recovery
Not used
srst
202
Circuit
lptd
PXB4219 / PXB4220 / PXB4221
Configuration
lptu
Register Description
lprd
2002-05-06
Register
gim
lpru
8
0