w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 88

• Manufacturer Part Number: w83637hg
• Description: Winbond Lpc I/o Lpc I/o
• Manufacturer: Winbond Electronics Corp America

W83637HF/HG
Note:
Abbreviation explanation (in alphabetical order) –
BDLAB – Baud rate divisor latch access bit.
CLKSTP – Stop Smart Card interface's clock SCCLK.
CLKSTPL – Set SCCLK level when CLKSTP is "1".
EPE – Even parity enable.
ERDRI – Enable RBR (Receiver Buffer Register) data ready interrupt.
ESCPTI - Enable SCPSNT interrupt.
ESCSRI - Enable interrupts of SCSR (read only Smart Card Status Register at base address + 5)
events.
ETBREI – Enable TBR (write only Transmitter Buffer Register at base address + 0) empty interrupt.
INTS2 ~ INTS0 – Interrupt status bits. Refer to description of ISR (read only Interrupt Status Register
at base address + 2) for details.
NSER – No stop bit error.
OER – Overrun error.
PBE – Parity bit enable.
PBER – Parity bit error.
RDR – Receiver data ready status.
RxFEI – Receiver FIFO error indication.
RxFRST – Receiver FIFO reset.
RxTL1 ~ RxTL0 – Receiver threshold level setting bits. Refer to description of SCFR (write only
Smart Card FIFO control register at base address + 2) for details.
SBD – Silent byte detected.
SCIODIR – SCIO direction bit (0/1 mean output/input respectively).
SCKFS1 ~ SCKFS0 – Smart Card interface clock frequency selection bits. Refer to description of
ECR (Extended Control Register at base address + 7) for details.
SCPTI – SCPSNT toggle interrupt status.
SC_SEL – Smart Card socket selection.
TBRE – TBR (write only Transmitter Buffer Register at base address + 0) empty status.
TSRE – TSR (Transmitter shift register) empty status.
TxFRST – Transmitter FIFO reset.
Publication Release Date: March, 2006
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Revision 1.6