w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 99

• Manufacturer Part Number: w83637hg
• Description: Winbond Lpc I/o Lpc I/o
• Manufacturer: Winbond Electronics Corp America

7.3 Smart Card ID Number (base address + 2 when BDLAB = 1, fixed at 70h)
This register contains a specific value of 70h for driver to identify Smart Card interface.
7.4 Functional Description
The following description uses abbreviations to refer to control/status registers and their contents of
Smart Card interface as seen in section 2.2. Also, PnP resources of Smart Card interface are assumed
to have been programmed and allocated appropriately by system BIOS.
7.5 Initialization
User needs to program control registers so that ATR (Answer To Reset) data streams can be properly
decoded after card insertion. Initialization settings include the following steps where sequential order
is irrelevant.
1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default
2. GTR is programmed with 01h for one stop bit.
3. Set SCFR bit 1 to "1" to enable FIFO.
4. PBE needs to be "1" for parity bit enable but EPE is optional.
5. Set SDIODIR to "1" to put SDIO in reception mode.
6. Set SCKFS1 and SCKFS0 to "01" to select 3 MHz for SCCLK.
Most default values of above control bits are designed as specified in initialization step but it is
recommended that user performs all the initialization sequence to avoid any ambiguity.
The relationship between transmission factors and settings of BLH, BLL and CBR is best described in
the following example.
Therefore,
7.6 Activation
Card insertion pulls up SCPSNT (assuming SCPSNT is active high with CRF0 bit 0 SCPSNT_POL = 0)
and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after
a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually
applied.
SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and
pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles
to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3).
transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3.
1
etu
Dd
Fd
=
D
F
=
×
372
1
1
f
=
(
BLH
(f means SCCLK frequency)
,
BLL
- 94 -
)
×
CBR
=
31
×
Publication Release Date: March, 2006
12
W83637HF/HG
Revision 1.6