w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 93

• Manufacturer Part Number: w83637hg
• Description: Winbond Lpc I/o Lpc I/o
• Manufacturer: Winbond Electronics Corp America

Smart Card FIFO control Register (SCFR at base address + 2 when BDLAB = 0, write only)
This register controls FIFO function of Smart Card interface.
Bit 7, 6: RxTL1 and RxTL0 mean receiver FIFO active threshold level control bits. These two bits are
Bit 5 ~ 3: Reserved.
Bit 2: TxFRST means transmitter FIFO reset control bit. Setting this bit to a logical "1" resets the
Bit 1: RxFRST means receiver FIFO reset control bit. Setting this bit to a logical "1" resets the
Bit 0: This bit enables FIFO of Smart Card interface. It should be set to a logical "1" before other bits
transmitter FIFO counter to initial state. This bit is self-cleared to "0" after being set to "1".
Default is "0".
receiver FIFO counter to initial state.
Default is "0".
of SCFR are programmed. Default is "0".
used to set the active level for the receiver FIFO interrupt. For example, if the interrupt active
level is set as 4 bytes, once there are at least 4 data characters in the receiver FIFO, an
interrupt is activated to notify host to read data from FIFO. Default to be 00b.
RxTL1
7
0
0
1
1
6
5
RxTL0
4
0
1
0
1
3 2
Rx FIFO Interrupt Active Level (Bytes)
1
This bit is self-cleared to "0" after being set to "1".
0
- 88 -
Enable FIFO
RxFRST
TxFRST
Reserved
Reserved
Reserved
RxTL0
RxTL1
01
04
08
14
Publication Release Date: March, 2006
W83637HF/HG
Revision 1.6