w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 91

• Manufacturer Part Number: w83637hg
• Description: Winbond Lpc I/o Lpc I/o
• Manufacturer: Winbond Electronics Corp America

Bit 2: ESCSRI means interrupt enable bit for SCSR-related events such as silent byte detected error,
Bit 1: ETBREI means interrupt enable bit for TBR (Transmitter Buffer Register) empty condition. An
Bit 0: ERDRI means interrupt enable bit for receiver data ready status. The active FIFO threshold level
Interrupt Status Register (ISR at base address + 2 when BDLAB = 0, read only)
This register contains mainly interrupt status including transmission-related interrupts and SCPSNT
toggle interrupt. Transmission-related interrupt status is coded and prioritized as in UART
implementation. User may also find FIFO enable/disabled status reflecting what is set in bit 0 of SCFR
(write only Smart Card FIFO Register at base address + 2 when BDLAB = 0) and SCPSNT line status.
no stop bit error, parity bit error or overrun error. Any SCSR-related event as described above
will trigger an interrupt if this bit is set to "1".
interrupt is issued when TBR is empty and this bit is set to "1". It is used in output mode
(SDIODIR = 0) to request host's attention to transfer data byte to card.
for this kind of interrupt when FIFO is enabled is specified in RxTL1 and RxTL0 (bit 7 and bit 6 of
SCFR at base address + 2. Refer to description of SCFR for details). An interrupt is issued if a
data byte is ready for host to read when FIFO is disabled or incoming data from card reaches
active FIFO threshold level when FIFO is enabled.
= 0
= 1
= 0
= 1
= 0
= 1
SCSR-related event interrupt is disabled.
SCSR-related event interrupt is enabled.
TBR empty interrupt is disabled.
TBR empty interrupt is enabled.
Receiver data ready interrupt is disabled.
Receiver data ready interrupt is enabled.
7
6
5
4
3 2
1
0
- 86 -
Interrupt pending
INTS0
INTS1
INTS2
SCPTI
SCPSNT
FIFO enabled
FIFO enabled
Publication Release Date: March, 2006
W83637HF/HG
Revision 1.6