w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 97

• Manufacturer Part Number: w83637hg
• Description: Winbond Lpc I/o Lpc I/o
• Manufacturer: Winbond Electronics Corp America

Extended Control Register (ECR at base address + 7, default 12h)
This register contains reset control bits, clock frequency selection bits, clock stop control bits and SCIO
direction control bit.
Bit 7: Cold reset. Setting "1" to this bit turns off power to Smart Card interface by pulling up SCPWR#.
Bit 6: Reserved.
Bit 5, 4: SCKFS1 and SCKFS0 means SCCLK frequency selection bit 1 and 0. They selects working
Bit 3: CLKSTP means clock stop control bit. Setting "1" to this bit stops SCCLK at a voltage level
Bit 2: CLKSTPL means clock stop voltage level.
Bit 1: SDIODIR means SDIO direction.
SCCLK is stopped, SCRST# kept low, SCIO in input mode and SCLED is inactive. ECR's
SCIODIR, SCKFS1 and SCKFS0 control bits and control bits in CBR, GTR, BLH and BLL are
cleared to default values. User must write a "0" to this bit to recover to normal state.
clock frequency as following table. Default values are 01h.
specified by CLKSTPL (bit 2 of ECR).
= 0
= 1
= 0
= 1
SCCLK stops at low if CLKSTP is also set to "1".
SCCLK stops at high if CLKSTP is also set to "1".
SDIO is in output mode.
SDIO is in input mode.
7
6
SCKFS1, SCKFS0
5
4
00
01
10
11
3 2
1
0
- 92 -
SCCLK frequency
Warm reset
SCIODIR
CLKSTP
CLKSTPL
SCKFS0
SCKFS1
Reserved
Cold reset
1.5 MHz
3.0 MHz
6.0 MHz
12 MHz
Publication Release Date: March, 2006
W83637HF/HG
Revision 1.6