p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 26

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p87lpc778

Manufacturer Part Number
p87lpc778
Description
Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
Manufacturer
NXP Semiconductors
Datasheet

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Product data
8.7 I
Table 21:
Table 22:
The I
connected to the bus. The main features of the bus are:
The I
the I
necessary arbitration and framing error checks, includes clock stretching and a bus
timeout timer. The interface is synchronized to software either through polled loops or
interrupts. Refer to the application note AN422, in Section 4, entitled ‘Using the
8XC751 Microcontroller as an I
I
Six time spans are important in I
Bit
2
1
0
BPEN
0
0
1
1
2
2
C-bus interface and sample driver routines.
C-bus serial interface
Bidirectional data transfer between masters and slaves.
Serial addressing of slaves (no added wiring).
Acknowledgment after each transferred byte.
Multimaster bus.
Arbitration between simultaneously transmitting masters without corruption of
serial data on bus.
The MINIMUM HIGH time for SCL when this device is the master.
The MINIMUM LOW time for SCL when this device is a master. This is not very
important for a single-bit hardware interface like this one, because the SCL low
time is stretched until the software responds to the I
response time normally meets or exceeds the MIN LO time. In cases where the
software responds within MIN HI + MIN LO) time, Timer I will ensure that the
minimum time is met.
2
2
2
C-bus. The hardware is a single bit interface which in addition to including the
C-bus uses two wires (SDA and SCL) to transfer information between devices
C-bus subsystem includes hardware to simplify the software required to drive
Symbol
PWM2B
PWM1B
PWM0B
PWMCON1 - PWM control register 1 (address C8H) bit description
PWMCON1 brake condition
Rev. 01 — 31 March 2004
BKCH
0
1
0
1
Value
0
1
0
1
0
1
2
C-bus Master’ for additional discussion of the 87C77x
2
C-bus operation and are insured by Timer I:
Description
PWM2 is HIGH, when Brake is asserted.
PWM1 is HIGH, when Brake is asserted.
PWM0 is HIGH, when Brake is asserted.
PWM2 is LOW, when Brake is asserted.
PWM1 is LOW, when Brake is asserted.
PWM0 is LOW, when Brake is asserted.
Brake condition
Set software break.
On when PWM not running (Brake Pin has no
effect).
On when Brake Pin asserted (PWM run has no
effect).
Clear software Brake.
CMOS single-chip 8-bit microcontroller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2
C-bus flags. The software
P87LPC778
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