p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 27

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.7.1 I
The MAXIMUM SCL CHANGE time while an I
in progress between a start condition and the following stop condition. This time span
serves to detect a lack of software response on this device as well as external
I
may mean a faulty device, or that noise induced onto the I
to withdraw from I
The first five of these times are 4.7 ms (see I
the low order three bits of Timer I. Timer I is clocked by the 87LPC77987 CPU clock.
Timer I can be pre-loaded with one of four values to optimize timing for different
oscillator frequencies. At lower frequencies, software response time is increased and
will degrade maximum performance of the I
I2CFG description for prescale values (CT0, CT1).
The MAXIMUM SCL CHANGE time is important, but its exact span is not critical. The
complete 10 bits of Timer I are used to count out the maximum time. When I
operation is enabled, this counter is cleared by transitions on the SCL pin. The timer
does not run between I
recently than the last start). When this counter is running, it will carry out after 1020 to
1023 machine cycles have elapsed since a change on SCL. A carry out causes a
hardware reset of the I
lack of software response by this device, the reset releases SCL and allows I
operation among other devices to continue.
If I
will occur whenever the ATN flag is set by a start, stop, arbitration loss, or data ready
condition (refer to the description of ATN following). In practice, it is not efficient to
operate the I
routine would somehow have to distinguish between hundreds of possible conditions.
Also, since I
the code simply waits for the I
Typically, the I
idle slave device, or a stop condition at an idle master device (if it is waiting to use the
I
aforementioned conditions.
Table 23:
Bit addressable
[1]
2
2
2
•
•
•
Bit
Symbol (R)
Symbol (W) CXA
C-bus problems. SCL ‘stuck low’ indicates a faulty master or slave. SCL ‘stuck high’
C-bus interrupts
C-bus). This is accomplished by enabling the I
2
The MINIMUM SCL HIGH TO SDA HIGH time in a stop condition.
The MINIMUM SDA HIGH TO SDA LOW time between I
conditions (4.7 ms, see I
The MINIMUM SDA LOW TO SCL LOW time in a start condition.
C-bus interrupts are enabled (EA and EI2 are both set to 1), an I
Due to the manner in which bit addressing is implemented in the 80C51 family, the I2CON register
should never be altered by use of the SETB, CLR, CPL, MOV (bit), or JBC instructions. This is due to
the fact that read and write functions of this register are different. Testing of I2CON bits via the JB and
JNB instructions is supported.
I2CON - I
2
2
C-bus can operate at a fairly high rate, the software may execute faster if
C-bus interface in this fashion because the I
2
[1]
RDAT
C-bus interrupt should only be used to indicate a start condition at an
; Reset value: 81H
7
2
Rev. 01 — 31 March 2004
C-bus arbitration.
2
C-bus control register (address D8H) bit allocation
2
ATN
IDLE
2
C-bus interface. In cases where the bus hang-up is due to a
C-bus frames (i.e., whenever reset or stop occurred more
6
2
C-bus specification).
2
C-bus interface.
DRDY
CDR
5
ARL
CARL
CMOS single-chip 8-bit microcontroller
4
2
2
C-bus. See special function register
C-bus specification) and are covered by
2
C-bus frame is in progress. A frame is
2
C-bus interrupt only during the
STR
CSTR
3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
2
2
STP
CSTP
C-bus interrupt service
C-bus caused all masters
2
C-bus stop and start
P87LPC778
2
MASTER -
XSTR
2
C-bus interrupt
1
2
2
C-bus
XSTP
C-bus
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