p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 33

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 31:
9397 750 12378
Product data
Description
External Interrupt 0
Timer0 Interrupt
External Interrupt 1
Timer1 Interrupt
Serial Port Tx and Rx
Brownout Detect
I
KBI Interrupt
Comparator 2 interrupt
Watchdog Timer
A/D Converter
Comparator 1 interrupt
Timer I interrupt
2
C-bus Interrupt
Summary of interrupts
8.8.1 External interrupt inputs
Interrupt
Flag Bit(s)
IE0
TF0
IE1
TF1
TI & RI
BOD
ATN
KBF
CMF2
WDOVF
ADCI
CMF1
-
Table 31
priority bits, arbitration ranking, and whether each interrupt may wake up the CPU
from Power-down mode.
The P87LPC778 has two individual interrupt inputs as well as the Keyboard Interrupt
function. The latter is described separately elsewhere in this section. The two
interrupt inputs are identical to those present on the standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or transition-activated
by setting or clearing bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is
triggered by a detected low at the INTn pin. If ITn = 1, external interrupt n is edge
triggered. In this mode if successive samples of the INTn pin show a high in one cycle
and a low in the next cycle, interrupt request flag IEn in TCON is set, causing an
interrupt request.
Since the external interrupt pins are sampled once each machine cycle, an input high
or low should hold for at least 6 CPU Clocks to ensure proper sampling. If the
external interrupt is transition-activated, the external source has to hold the request
pin high for at least one machine cycle, and then hold it low for at least one machine
cycle. This is to ensure that the transition is seen and that interrupt request flag IEn is
set. IEn is automatically cleared by the CPU when the service routine is called.
If the external interrupt is level-activated, the external source must hold the request
active until the requested interrupt is actually generated. If the external interrupt is still
asserted when the interrupt service routine is completed another interrupt will be
generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level
sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the P87LPC778 is put into Power-down or
Idle mode, the interrupt will cause the processor to wake up and resume operation.
Refer to
Section 8.12 “Power reduction modes” on page 43
summarizes the interrupt sources, flag bits, vector addresses, enable bits,
Vector
Address
0003h
000Bh
0013h
001Bh
0023h
002Bh
0033h
003Bh
0043h
0053h
005Bh
0063h
0073h
Rev. 01 — 31 March 2004
Interrupt
Enable Bit(s)
EX0 (IEN0.0)
ET0 (IEN0.1)
EX1 (IEN0.2)
ET1 (IEN0.3)
ES (IEN0.4)
EBO (IEN0.5)
EI2 (IEN1.0)
EKB (IEN1.1)
EC2 (IEN1.2)
EWD (IEN0.6)
EAD (IEN1.4)
EC1 (IEN1.5)
ETI (IEN1.7)
Interrupt
Priority
IP0H.3, IP0.3
IP1H.7, IP1.7
IP0H.0, IP0.0
IP0H.1, IP0.1
IP0H.2, IP0.2
IP0H.4, IP0.4
IP0H.5, IP0.5
IP1H.0, IP1.0
IP1H.1, IP1.1
IP1H.2, IP1.2
IP0H.6, IP0.6
IP1H.4, IP1.4
IP1H.5, IP1.5
CMOS single-chip 8-bit microcontroller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Arbitration
Ranking
1 (highest)
4
7
10
12
2
5
8
11
3
6
9
13 (lowest)
for details.
P87LPC778
Power-down
Wake-up
Yes
No
Yes
No
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
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