p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 64

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.16.1 Watchdog feed sequence
8.16.2 Watchdog reset
If the Watchdog timer is running, it must be fed before it times out in order to prevent
a chip reset from occurring. The Watchdog feed sequence consists of first writing the
value 1Eh, then the value E1h to the WDRST register. An example of a Watchdog
feed sequence is shown below.
WDFeed:
The two writes to WDRST do not have to occur in consecutive instructions. An
incorrect Watchdog feed sequence does not cause any immediate response from the
Watchdog timer, which will still time out at the originally scheduled time if a correct
feed sequence does not occur prior to that time.
After a chip reset, the user program has a limited time in which to either feed the
Watchdog timer or change the timeout period. When a low CPU clock frequency is
used in the application, the number of instructions that can be executed before the
Watchdog overflows may be quite small.
If a Watchdog reset occurs, the internal reset is active for approximately one
microsecond. If the CPU clock was still running, code execution will begin
immediately after that. If the processor was in Power-down mode, the Watchdog reset
will start the oscillator and code execution will resume after the oscillator is stable.
Table 55:
Not bit addressable; Reset value: 30H for a Watchdog reset; 10H for other reset sources if the
Watchdog is enabled via the WDTE configuration bit; 00H for other reset sources if the
Watchdog is disabled via the WDTE configuration bit.
Table 56:
Bit
7, 6
5
4
3
2 to 0
Bit
Symbol
mov
mov
Symbol
-
WDOVF
WDRUN
WDCLK
WDS[2:0]
WDCON - Watchdog timer control register (address A7H) bit allocation
WDCON - Watchdog timer control register (address A7H) bit description
WDRST,#1eh
WDRST,#0e1h
7
-
Rev. 01 — 31 March 2004
6
-
Description
Reserved for future use. Should not be set to ‘1’ by user programs.
Watchdog timer overflow flag. Set when a Watchdog reset or timer
overflow occurs. Cleared when the Watchdog is fed.
Watchdog run control. The Watchdog timer is started when
WDRUN = 1 and stopped when WDRUN = 0. This bit is forced to
‘1’ (Watchdog running) if the WDTE configuration bit = 1.
Watchdog clock select. The Watchdog timer is clocked by CPU
clock / 6 when WDCLK = 1 and by the Watchdog RC oscillator
when WDCLK = 0. This bit is forced to 0 (using the Watchdog RC
oscillator) if the WDTE configuration bit = 1.
Watchdog rate select.
; First part of Watchdog feed sequence.
; Second part of Watchdog feed sequence.
WDOVF
5
WDRUN
4
CMOS single-chip 8-bit microcontroller
WDCLK
3
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
WDS2
P87LPC778
2
WDS1
1
WDS0
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