km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet
km416rd8ac
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km416rd8ac Summary of contents
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... KM416RD8AC(D)/KM418RD8AC(D) 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAM TM Revision 1.01 October 1999 Page -2 ™ Direct RDRAM Rev. 1.01 Oct. 1999 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Revision History Version 1.0 (July 1999) - Preliminary - Based on the Rambus Datasheet 1.0 ver. Version 1.01 (October 1999) On page 1 - Delete the part numbers of low power. On page 32 - Add the data of CNFGA Register @ Figure 28. On page 33 - Add the data of CNFGB Register @ Figure 29 and correct the CORG4..0 field of CNFGB register. ...
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... KM416RD8AC(D)/KM418RD8AC(D) ORDERING INFORMATION SAMSUNG Memory Device Organization Product Density 1. SAMSUNG Memory 2. Device - 4 : DRAM 3. Organization - 16 : x16 bit - 18 : x18 bit 4. Product - RD : Direct RAMBUS DRAM 5. Density - 16M - 32 : 32M 6. Revision - Blank : 1st Gen 2nd Gen ...
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... RDRAM core uses Normal Power Self Refresh. Rev. 1.01 Oct. 1999 Page 1 ™ SEC KOREA KM4xxRD8AD M b. Mirrored Package Part Number b c KM416RD8AC(D )-R G60 KM416RD8AC(D)-RK70 KM416RD8AC(D)-RK80 KM418RD8AC(D)-RG60 KM418RD8AC(D)-RK70 KM418RD8AC(D)-RK80 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Pinouts and Definitions Normal Package This table shows the pin assignments of the normal RDRAM package. Table Center-Bonded Device GND VDD 12 11 DQA7 DQA4 CFM CFMN 10 9 GND VDD GND GNDa 8 CMD DQA5 DQA2 VDDa SCK DQA6 DQA1 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Table 3: Pin Description Signal I/O Type a SIO1,SIO0 I/O CMOS a CMD I CMOS a SCK I CMOS DDa V CMOS GND GNDa b DQA8..DQA0 I/O RSL b CFM I RSL b CFMN I RSL V REF b CTMN I RSL b CTM I RSL b RQ7..RQ5 or I RSL ROW2..ROW0 b RQ4..RQ0 or I RSL COL4..COL0 b DQB8 ...
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... KM416RD8AC(D)/KM418RD8AC(D) RQ7..RQ5 or DQB8..DQB0 ROW2..ROW0 3 9 RCLK 1:8 Demux Packet Decode ROWR ROWA ROP Match Mux DM Row Decode PRER ACT Sense Amp 32x72 Internal DQB Data Path Figure 2: 128/144 Mbit Direct RDRAM Block Diagram ...
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... KM416RD8AC(D)/KM418RD8AC(D) General Description Figure block diagram of the 128/144 Mbit Direct RDRAM. It consists of two major blocks: a “core” block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core ...
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... KM416RD8AC(D)/KM418RD8AC(D) Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 4 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM ...
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... KM416RD8AC(D)/KM418RD8AC( CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 ROW1 DR4F DR1 BR1 BR4 RsvR R7 ROW0 DR3 DR0 BR2 RsvB AV=1 R6 ROWA Packet CTM/CFM S=1 DC4 COL4 DC3 COL3 DC2 COP1 COL2 DC1 COP0 COL1 DC0 COP2 COP3 BC3 BC0 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Field Encoding Summary Table 6 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a ...
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... KM416RD8AC(D)/KM418RD8AC(D) Table 8 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 17 for a more detailed description ...
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... KM416RD8AC(D)/KM418RD8AC(D) DQ Packet Timing Figure 4 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as ...
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... KM416RD8AC(D)/KM418RD8AC( CTM/CFM ROW2 ACT a0 ..ROW0 COL4 WR a1 ..COL0 DQA8..0 DQB8..0 Transaction {Da,Ba,Ra} COLM Packet CTM/CFM COL4 MA7 MA5 MA3 MA1 COL3 M=1 MA6 MA4 MA2 MA0 COL2 MB7 MB4 MB1 ...
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... KM416RD8AC(D)/KM418RD8AC(D) ROW-to-ROW Packet Interaction CTM/CFM ROW2 ROPa a0 ROPb b0 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0 Transaction a: ROPa a0 = {Da,Ba,Ra} Transaction b: ROPb b0= {Db,Bb,Rb} Figure 6: ROW-to-ROW Packet Interaction- Timing Figure 6 shows two packets on the ROW pins separated by ...
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... KM416RD8AC(D)/KM418RD8AC(D) ROW-to-ROW Interaction - contin- ued Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, t applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the t Two adjacent banks can’ ...
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... KM416RD8AC(D)/KM418RD8AC(D) COL-to-COL Packet Interaction CTM/CFM ROW2 ..ROW0 t CCDELAY COL4 COPa a1 COPb b1 ..COL0 DQA8..0 DQB8..0 Transaction a: COPa a1 = {Da,Ba,Ca1} Transaction b: COPb b1 = {Db,Bb,Cb1} Transaction c: COPc c1 = {Dc,Bc,Cc1} Figure 8: COL-to-COL Packet Interaction- Timing Figure 8 shows three arbitrary packets on the COL pins. Packets “ ...
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... KM416RD8AC(D)/KM418RD8AC(D) COL-to-ROW Packet Interaction CTM/CFM ROW2 ROPb b0 ..ROW0 COL4 COPa a1 ..COL0 DQA8..0 DQB8..0 Transaction a: COPa a1= {Da,Ba,Ca1} Transaction b: ROPb b0= {Db,Bb,Rb} Figure 9: COL-to-ROW Packet Interaction- Timing Figure 9 shows arbitrary packets on the COL and ROW pins. ...
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... KM416RD8AC(D)/KM418RD8AC(D) ROW-to-ROW Examples Figure 10 shows examples of some of the ROW-to-ROW packet spacings from Table 10. A complete sequence of acti- vate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the t and t timing parameters, the separation ...
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... KM416RD8AC(D)/KM418RD8AC(D) Figure 12 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table 10. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be ...
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... KM416RD8AC(D)/KM418RD8AC(D) Precharge Mechanisms Figure 13 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time CTM/CFM ROW2 ACT a0 ..ROW0 COL4 ..COL0 t RAS DQA8..0 DQB8.. Figure 13: Precharge via PRER Command in ROWR Packet Figure 14 (top) shows an example of precharge with a RDA command ...
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... KM416RD8AC(D)/KM418RD8AC(D) COLC Packet: RDA Precharge Offset CTM/CFM The RDA precharge is equivalent to a PRER command here ROW2 ACT a0 ..ROW0 COL4 RD a1 ..COL0 DQA8..0 DQB8..0 Transaction a: RD COLC Packet: WDA Precharge Offset ...
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... KM416RD8AC(D)/KM418RD8AC(D) Read Transaction - Example Figure 15 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time t later command is issued in a RCD COLC packet. Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and column address (abbreviated as a1) ...
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... KM416RD8AC(D)/KM418RD8AC(D) Write Transaction - Example Figure 16 shows an example of a write transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time t -t later command is issued RCD RTR in a COLC packet (note that the t interval is measured to RCD the end of the COLC packet with the first retire command). ...
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... KM416RD8AC(D)/KM418RD8AC(D) Write/Retire - Examples The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of transporting the write command, write address, and write data into the write buffer. The second step happens when the RDRAM automatically retires the write buffer (with an optional bytemask) into the sense amp ...
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... KM416RD8AC(D)/KM418RD8AC(D) Write/Retire Examples - continued The RD will prevent a retire of the first WR from automati- cally happening. But the first dualoct D(a1) in the write buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued in the third COLC packet ...
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... KM416RD8AC(D)/KM418RD8AC(D) Interleaved Write - Example Figure 20 shows an example of an interleaved write transac- tion. Transactions similar to the one presented in Figure 16 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once every t rather than once every t interval (four times more often). ...
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... KM416RD8AC(D)/KM418RD8AC( CTM/CFM ROW2 ACT a0 ..ROW0 t RCD COL4 PREX y3 ..COL0 DQA8..0 Q (x2) Q (y1) Q (y2) DQB8..0 Transaction y: RD Transaction z: RD Transaction a: RD Transaction b: RD Transaction c: RD Transaction d: RD Transaction e: RD ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register Transactions The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the RDRAM. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the RDRAM ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register Packets Table 14 summarizes the formats of the four packet types for control register transactions. Table 15 summarizes the fields that are used within the packets. Figure 25 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands ...
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... KM416RD8AC(D)/KM418RD8AC(D) Initialization T 0 SCK CMD 0000 1100 00000000...00000000 SIO0 0000000000000000 The packet is repeated from SIO0 to SIO1 SIO1 0000000000000000 Figure 26: SIO Reset Sequence Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by using a sequence of control register transactions on the serial CMOS pins ...
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... KM416RD8AC(D)/KM418RD8AC(D) 3.13 Write CCA and CCB Register - These registers are written with a value halfway between their minimum and maximum values. This shortens the time needed for the RDRAMs to reach their steady-state current control values in stage 5.0. 3.14 Powerdown Exit - The RDRAMs are in the PDN power state at this point ...
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... KM416RD8AC(D)/KM418RD8AC(D) S28IECO=1: Upon powerup the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization proce- dure for more information on how to handle this in a system. Initialization Note [3]: After the step of equalizing the total read delay of each RDRAM has been completed (i ...
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... KM416RD8AC(D)/KM418RD8AC(D) SA11..SA0 Register Field read-write/ read-only 045 NAPX NAPXA read-write, 5 bits 16 NAPX read-write, 5 bits DQS read-write, 1 bits 046 PDNXA PDNXA read-write, 13 bits 16 047 PDNX PDNX read-write, 13 bits 16 048 TPARM TCAS read-write, 2 bits 16 TCLS read-write, 2 bits TCDLY0 read-write, 3 bits 049 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register: INIT SDE 0 0 VID DIS TSQ TEN LSR PSR NSR SRP PSX 5 Control Register: CNFGA PVER5..0 MVER5..0 = 000001 = 010000 Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register: CNFGB SVER5..0 CORG4..0 = 00000 = 00100 Control Register: TEST34 Read/write register. Reset value of TEST34 is zero (from SIO Reset) This register are used for testing purposes. It must not be read or written after SIO Reset ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register: REFB Read/write register. Reset value is zero (from SETR/CLRR). Refresh Bank register. REFB4..REFB0 is the bank that will be refreshed next during self-refresh. REFB4..0 is incremented after each self-refresh activate and precharge operation pair ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register: NAPX DQS NAPX4..0 Control Register: PDNXA PDNXA12..0 Read/write register. Reset value is undefined PDNXA4..0 - PDN Exit Phase A. This field specifies the number of (64•SCK cycle) units during the first phase for exiting PDN mode. It must satisfy: PDNXA• ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register: TPARM TCDLY0 Read/write register. Reset value is undefined. TCAS1..0 - Specifies the t core parameter in CAS-C units. This should be “10” CYCLE TCLS1..0 - Specifies the t core parameter in CLS-C units. Should be “10” ...
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... KM416RD8AC(D)/KM418RD8AC(D) Control Register: SKIP MSE Read/write register (except AS field). Reset value is zero (SIO Reset Autoskip. Read-only value determined by autoskip circuit and stored when SETF serial command is received by RDRAM during initialization. In figure ...
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... KM416RD8AC(D)/KM418RD8AC(D) Power State Management Table 17 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1 ...
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... KM416RD8AC(D)/KM418RD8AC(D) able to frame COL packets (TFRM is a control register field - see Figure 40). Once in ATTN state, the RDRAM will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands. automatic ATTNR automatic ATTN NAPR • RLXR PDEV.CMD•SIO0 NAPR • RLXR PDEV.CMD• ...
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... KM416RD8AC(D)/KM418RD8AC(D) PDEV5..0 address packet and exits NAP or PDN when the wake-up sequence is presented on the CMD wire. The ROW and COL pins must be quiet at a time t S4 cated falling SCK edge (timed with the PDNX or NAPX register fields). After that, ROW and COL packets may be directed to the RDRAM which is now in ATTN or STBY state ...
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... KM416RD8AC(D)/KM418RD8AC( CTM/CFM If PSX=1 in Init register, then ROW2 NAP/PDN exit is broadcast (no PDEV field). ..ROW0 COL4 ..COL0 DQA8..0 b PDEV5..0 PDEV5..0 DQB8.. b,c DQS=0 SCK CMD 0 1 SIO0 a 0/1 The packet is repeated ...
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... KM416RD8AC(D)/KM418RD8AC(D) Refresh RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure 50 shows an example of this. The REFA command in the transaction is typically a broad- cast command (DR4T and DR4F are both set in the ROWR ...
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... KM416RD8AC(D)/KM418RD8AC(D) Current and Temperature Control Figure 51 shows an example of a transaction which performs current control calibration necessary to perform this operation once to every RDRAM in every t order to keep the I output current in its proper range. OL This example uses four COLX packets with a CAL command ...
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... KM416RD8AC(D)/KM418RD8AC(D) Electrical Conditions Symbol Parameter and Conditions T Junction temperature under bias Supply voltage DD, DDA V V Supply voltage droop (DC) during NAP interval (t DD,N, DDA Supply voltage ripple (AC) during NAP interval (t DD,N, DDA,N V Supply voltage for CMOS pins (2.5V controllers) CMOS Supply voltage for CMOS pins (1.8V controllers) ...
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... KM416RD8AC(D)/KM418RD8AC(D) Symbol Parameter t t SIO0, SIO1 input rise and fall times DR1, DF1 t t CMD, SCK input rise and fall times DR2, DF2 t SCK cycle time - Serial control register transactions CYCLE1 SCK cycle time - Power transitions SCK high and low times ...
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... KM416RD8AC(D)/KM418RD8AC(D) Electrical Characteristics Symbol Parameter and Conditions Junction-to-Case thermal resistance current @ V REF REF REF,MAX I RSL output high current @ ( RSL I current @ V ALL RSL I current resolution step Dynamic output impedance OUT I CMOS input leakage current @ (0 V I,CMOS ...
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... KM416RD8AC(D)/KM418RD8AC(D) RSL - Clocking Figure timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. t CYCLE t CL CTM V X- ...
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... KM416RD8AC(D)/KM418RD8AC(D) RSL - Receive Timing Figure timing diagram which shows the detailed requirements for the RSL input signals on the Channel. The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the Channel. Each signal is sampled twice per t ...
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... KM416RD8AC(D)/KM418RD8AC(D) RSL - Transmit Timing Figure timing diagram which shows the detailed requirements for the RSL output signals on the Channel. The DQA and DQB signals are outputs to transmit informa- tion that is received by a Direct RAC on the Channel. Each signal is driven twice per t interval ...
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... KM416RD8AC(D)/KM418RD8AC(D) CMOS - Receive Timing Figure timing diagram which shows the detailed requirements for the CMOS input signals. The CMD and SIO0 signals are inputs which receive infor- mation transmitted by a controller or by another RDRAM’s SIO1 output. SCK is the CMOS clock signal driven by the controller ...
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... KM416RD8AC(D)/KM418RD8AC(D) The SCK clock is also used for sampling data on RSL inputs in one situation. Figure 48 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (see Figure 27), then the PDN and NAP exit sequences are broad- cast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed ...
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... KM416RD8AC(D)/KM418RD8AC(D) CMOS - Transmit Timing Figure timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per t interval on the falling edge. The CYCLE1 SCK t Q1,MAX SIO0 t QF1 SIO0 or SIO1 t DF1 SIO1 or SIO0 t QF1 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Figure 58 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The t parameter specified this propagation PROP1 delay. The rise and fall times of SIO0 and SIO1 inputs must be t and t , measured at the 20% and 80% levels. The ...
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... KM416RD8AC(D)/KM418RD8AC(D) Timing Parameters Parameter Description t Row Cycle time of RDRAM banks -the interval between ROWA packets with RC ACT commands to the same bank. t RAS-asserted time of RDRAM bank - the interval between ROWA packet RAS with ACT command and next ROWR packet with PRER same bank ...
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... KM416RD8AC(D)/KM418RD8AC(D) Absolute Maximum Ratings Symbol Parameter V Voltage applied to any RSL or CMOS pin with respect to Gnd I,ABS Voltage on VDD and VDDA with respect to Gnd DD,ABS DDA,ABS T Storage temperature STORE I - Supply Current Profile DD I value RDRAM blocks consuming power DD I Self-refresh only for INIT.LSR=0 ...
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... KM416RD8AC(D)/KM418RD8AC(D) Capacitance and Inductance Figure 60 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device presents to the Channel. Figure 60: Equivalent Load Circuit for RSL Pins Pad Pad ...
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... KM416RD8AC(D)/KM418RD8AC(D) This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling effects make the effective single-pin inductance L capacitance function of neighboring pins, these param- I eters are intrinsically data-dependent. For purposes of speci- fying the device electrical loading on the Channel, the ...
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... KM416RD8AC(D)/KM418RD8AC(D) Center-Bonded uBGA Package Figure 61 shows the form and dimensions of the recom- mended package for the center-bonded CSP device class Figure 61: Center-Bonded uBGA Package Symbol The E,MAX parameter for SO-RIMM applications is 0.94mm. ...
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... KM416RD8AC(D)/KM418RD8AC(D) Glossary of Terms Activate command from AV field. ACT To access a row and place in sense amp. activate Two RDRAM banks which share sense adjacent amps (also called doubled banks). ASYM CCA register field for RSL V Power state - ready for ROW/COL ATTN packets. ...
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... KM416RD8AC(D)/KM418RD8AC(D) No-operation command in XOP field. NOXOP NSR INIT register field- NAP self-refresh. A collection of bits carried on the Channel. packet PDN Power state - needs SCK/CMD wakeup. Powerdown command in ROP field. PDNR Control register - PDN exit delay A. PDNXA Control register - PDN exit delay B. ...
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... KM416RD8AC(D)/KM418RD8AC(D) Table Of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features Key Timing Parameters/Part Numbers . . . . . . . . . . . 1 Pinouts and Definitions . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7 Field Encoding Summary . . . . . . . . . . . . . . . . . . . . .8-9 DQ Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 COLM Packet to D Packet Mapping . . . . . . . . . .10-11 ROW-to-ROW Packet Interaction . . . . . . . . . . . .12-13 ROW-to-COL Packet Interaction . . . . . . . . . . . . . . . 13 COL-to-COL Packet Interaction . . . . . . . . . . . . . . . . 14 COL-to-ROW Packet Interaction ...