km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 56

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The t
delay. The rise and fall times of SIO0 and SIO1 inputs must
be t
rise and fall times of SIO0 and SIO1 outputs are t
t
RSL - Domain Crossing Window
When read data is returned by the RDRAM, information
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t
DQA/B
DQA/B
DQA/B
DQA/B
DQA/B
DQA/B
DQA/B
DQA/B
DQA/B
QF1
CFM
COL
CTM
CTM
CTM
CTM
CTM
DR1
, measured at the 20% and 80% levels.
and t
t
TR
t
t
TR
t
TR
DF1
TR
t
TR
PROP1
, measured at the 20% and 80% levels. The
Case A’
Case E’
Case B’
Case D’
Case A
Case C
Case D
Case E
Case B
DCW
parameter specified this propagation
is needed in order to describe how
t
t
RD a1
t
t
t
t
t
t
t
TR
TR
TR
TR
TR
TR
TR
TR
TR
=t
=t
=0
=t
=t
=t
=t
=0.5•t
=0
Figure 59: RSL Transmit - Crossing Read Domains
CYCLE
CYCLE
DCW,MAX
DCW,MAX
CYCLE
CYCLE
TR
parameter permits
CYCLE
+t
+t
DCW,MIN
DCW,MIN
QR1
and
Page 53
the delay between a RD command packet and read data
packet varies as a function of the t
Figure 59 shows this timing for five distinct values of t
Case A (t
ment. The delay between the RD command and read data is
t
E), the command to data delay is (t
value is in the range 0 to t
delay can also be (t
A’ and B’ (the gray packets). Similarly, when the t
is in the range (t
to data delay can also be (t
as cases D’ and E’ (the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.
CAC
t
t
t
t
t
t
t
t
CAC
t
CAC
CAC
CAC
CAC
CAC
CAC
CAC
CAC
. As t
-t
-t
-t
-t
-t
-t
-t
-t
-t
TR
TR
TR
TR
TR
TR
TR
TR
TR
TR
TR
+t
-t
+t
=0) is what has been used throughout this docu-
-t
CYCLE
varies from zero to t
CYCLE
CYCLE
CYCLE
CYCLE
CAC
+t
-t
TR
DCW,MIN
DCW,MAX
CAC
-t
CYCLE
Rev. 1.01 Oct. 1999
Direct RDRAM
-t
TR
CYCLE
) to t
TR
+t
CAC
). This is shown as cases
, the command to data
Q(a1)
CYCLE
value.
Q(a1)
Q(a1)
CYCLE
Q(a1)
-t
TR
(cases A through
Q(a1)
). When the t
). This is shown
t
CYCLE
, the command
Q(a1)
Q(a1)
Q(a1)
Q(a1)
TR
value
TR
TR
.
™