km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 27

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
Interleaved Write - Example
Figure 20 shows an example of an interleaved write transac-
tion. Transactions similar to the one presented in Figure 16
are directed to non-adjacent banks of a single RDRAM. This
allows a new transaction to be issued once every t
rather than once every t
The DQ data pin efficiency is 100% with this sequence.
With two dualocts of data written per transaction, the COL,
DQA, and DQB pins are fully utilized. Banks are precharged
Interleaved Read - Example
Figure 21 shows an example of interleaved read transac-
tions. Transactions similar to the one presented in Figure 15
are directed to non-adjacent banks of a single RDRAM. The
address sequence is identical to the one used in the previous
write example. The DQ data pins efficiency is also 100%.
The only difference with the write example (aside from the
use of the RD command rather than the WR command) is
the use of the PREX command in a COLX packet to
precharge the banks rather than the RDA command. This is
done because the PREX is available for a readtransaction but
is not available for a masked write transaction.
Interleaved RRWW - Example
Figure 22 shows a steady-state sequence of 2-dualoct
RD/RD/WR/WR.. transactions directed to non-adjacent
banks of a single RDRAM. This is similar to the interleaved
write and read examples in Figure 20 and Figure 21 except
COL4
CTM/CFM
DQA8..0
ROW2
DQB8..0
..COL0
..ROW0
D (x2)
T
0
T
MSK (y1)
1
WR z1
T
2
ACT a0
T
3
RC
Figure 20: Interleaved Write Transaction with Two Dualoct Data Length
Transaction b: WR
Transaction d: WR
D (y1)
Transaction y: WR
Transaction z: WR
Transaction a: WR
Transaction c: WR
Transaction e: WR
T
Transaction f: WR
4
interval (four times more often).
T
MSK (y2)
5
WRA z2
T
6
T
7
D (y2)
T
t
8
RCD
T
MSK (z1)
9
WR a1
T
10
ACT b0
T
11
T
D (z1)
12
b0 = {Da,Ba+2,Rb}
d0 = {Da,Ba+6,Rd}
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
c0 = {Da,Ba+4,Rc}
T
f0 = {Da,Ba+2,Rf}
13
MSK (z2)
a0 = {Da,Ba,Ra}
e0 = {Da,Ba,Re}
WRA a2
T
14
t
RR
T
CWD
15
T
D (z2)
interval
16
T
MSK (a1)
17
WR b1
T
18
ACT c0
T
19
Page 24
D (a1)
T
20
t
T
RC
MSK (a2)
21
WRA b2
b1 = {Da,Ba+2,Cb1}
d1 = {Da,Ba+6,Cd1}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
c1 = {Da,Ba+4,Cc1}
f1 = {Da,Ba+2,Cf1}
using the WRA autoprecharge option rather than the PRER
command in an ROWR packet on the ROW pins.
In this example, the first transaction is directed to device Da
and bank Ba. The next three transactions are directed to the
same device Da, but need to use different, non-adjacent
banks Bb, Bc, Bd so there is no bank conflict. The fifth
transaction could be redirected back to bank Ba without
interference, since the first transaction would have
completed by then (t
use any value of row address (Ra, Rb, ..) and column address
(Ca1, Ca2, Cb1, Cb2, ...).
that bubble cycles need to be inserted by the controller at
read/write boundaries. The DQ data pin efficiency for the
example in Figure 22 is 32/42 or 76%. If there were more
RDRAMs on the Channel, the DQ pin efficiency would
approach 32/34 or 94% for the two-dualoct RRWW
sequence (this case is not shown).
In Figure 22, the first bubble type t
controller between a RD and WR command on the COL
pins. This bubble accounts for the round-trip propagation
delay that is seen by read data, and is explained in detail in
Figure 4. This bubble appears on the DQA and DQB pins as
t
Q. This bubble also appears on the ROW pins as t
T
a1 = {Da,Ba,Ca1}
e1 = {Da,Ba,Ce1}
DBUB1
22
T
23
D (a2)
T
24
T
MSK (b1)
25
between a write data dualoct D and read data dualoct
WR c1
T
26
ACT d0
T
27
D (b1)
T
28
T
29
MSK (b2)
WRA c2
T
30
b2= {Da,Ba+2,Cb2}
d2= {Da,Ba+6,Cd2}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
c2= {Da,Ba+4,Cc2}
f2= {Da,Ba+2,Cf2}
T
RC
a2= {Da,Ba,Ca2}
e2= {Da,Ba,Ce2}
31
D (b2)
T
32
has elapsed). Each transaction may
T
33
t
MSK (c1)
RR
WR d1
T
34
ACT e0
T
Rev. 1.01 Oct. 1999
35
Direct RDRAM
T
D(c1)
36
T
MSK (c2)
37
CBUB1
WR d2
T
same bank as transaction a
38
Transaction e can use the
T
39
D (c2)
T
40
b3 = {Da,Ba+2}
d3 = {Da,Ba+6}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
c3 = {Da,Ba+4}
f3 = {Da,Ba+2}
is inserted by the
T
a3 = {Da,Ba}
e3 = {Da,Ba}
MSK (d1)
41
ACT f0
WR e1
T
42
T
43
D (d1)
T
RBUB1
44
T
45
MSK (d2)
WR e2
T
46
T
.
47
™
Q (d1)