km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 62

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
Glossary of Terms
ACT
activate
adjacent
ASYM
ATTN
ATTNR
ATTNW
AV
bank
BC
BBIT
broadcast
BR
bubble
BYT
BX
C
CAL
CBIT
CCA
CCB
CFM,CFMN
Channel
CLRR
CMD
CNFGA
CNFGB
COL
COL
COLC
COLM
column
command
COLX
Activate command from AV field.
To access a row and place in sense amp.
Two RDRAM banks which share sense
amps (also called doubled banks).
CCA register field for RSL V
Power state - ready for ROW/COL
packets.
Power state - transmitting Q packets.
Power state - receiving D packets.
Opcode field in ROW packets.
A block of 2
core of the RDRAM.
Bank address field in COLC packet.
CNFGA register field - # bank address
bits.
An operation executed by all RDRAMs.
Bank address field in ROW packets.
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
CNFGB register field - 8/9 bits per byte.
Bank address field in COLX packet.
Column address field in COLC packet.
Calibrate (I
CNFGB register field - # column address
bits.
Control register - current control A.
Control register - current control B.
Clock pins for receiving packets.
ROW/COL/DQ pins and external wires.
Clear reset command from SOP field.
CMOS pin for initialization/power control.
Control register with configuration fields.
Control register with configuration fields.
Pins for column-access control.
COLC,COLM,COLX packet on COL pins.
Column operation packet on COL pins.
Write mask packet on COL pins.
Rows in a bank or activated row in sense
amps have 2
A decoded bit-combination from a field.
Extended operation packet on COL pins.
OL
CBIT
RBIT
) command in XOP field.
•2
dualocts column storage.
CBIT
storage cells in the
OL
/V
OH
.
Page 59
controller
COP
core
CTM,CTMN
current control
D
DBL
DC
device
DEVID
DM
doubled-bank
DQ
DQA
DQB
DQS
DR,DR4T,DR4F
dualoct
DX
field
INIT
initialization
LSR
M
MA
MB
MSK
MVER
NAP
NAPR
NAPRC
NAPXA
NAPXB
NOCOP
NOROP
A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.
Column opcode field in COLC packet.
The banks and sense amps of an RDRAM.
Clock pins for transmitting packets.
I
Write data packet on DQ pins.
CNFGB register field - doubled-bank.
Device address field in COLC packet.
An RDRAM on a Channel.
Control register with device address that is
matched against DR, DC, and DX fields.
Device match for ROW packet decode.
RDRAM with shared sense amp.
DQA and DQB pins.
Pins for data byte A.
Pins for data byte B.
NAPX register field - PDN/NAP exit.
fields in ROWA and ROWR packets.
16 bytes - the smallest addressable datum.
Device address field in COLX packet.
A collection of bits in a packet.
Control register with initialization fields.
Configuring a Channel of RDRAMs so
they are ready to respond to transactions.
CNFGA register field - low-power self-
refresh.
Mask opcode field (COLM/COLX packet).
Field in COLM packet for masking byte A.
Field in COLM packet for masking byte B.
Mask command in M field.
Control register - manufacturer ID.
Power state - needs SCK/CMD wakeup.
Nap command in ROP field.
Conditional nap command in ROP field.
NAPX register field - NAP exit delay A.
NAPX register field - NAP exit delay B.
No-operation command in COP field.
No-operation command in ROP field.
OL
Periodic operations to update the proper
Device address field and packet framing
value of RSL output drivers.
Rev. 1.01 Oct. 1999
Direct RDRAM
™