km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 38

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64•SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Note - t
15 14 13 12 11 10 9
15 14 13 12 11 10 9
0
0
PDNXA•64•t
Control Register: PDNXA
Control Register: NAPX
0
0
SCYCLE
0
0
0
Figure 37: PDNXA Register
0
SCYCLE
is t
DQS
CYCLE1
8
8
NAPX4..0
t
PDNXA,MAX
(SCK cycle time).
PDNXA12..0
7
7
6
6
5
5
Address: 046
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0. See Figure 48 - This field must be written with a 1 for
this RDRAM.
4
4
Address: 045
NAPX•t
3
3
NAPXA4..0
2
2
Figure 36: NAPX Register
1
SCYCLE
1
16
0
0
16
Page 35
NAPXA•t
Read/write register.
Reset value is undefined
Note - t
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
Do not set this field to zero.
.
NAPXA•t
Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256•SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
If this equation can’t be satisfied, then the maximum
PDNX value should be written, and the t
window will be modified (see Figure 49)
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Note - t
15 14 13 12 11 10 9
0
PDNX•256•t
Control Register: PDNX
SCYCLE
0
SCYCLE
SCYCLE
0
SCYCLE
+t
Figure 38: PDNX Register
NAPXB,MAX
is t
SCYCLE
is t
CYCLE1
CYCLE1
t
NAPXA,MAX
(SCK cycle time).
8
PDNXA•64•t
Rev. 1.01 Oct. 1999
Direct RDRAM
(SCK cycle time).
t
7
PDNXB,MAX
PDNX12..0
6
5
Address: 047
4
SCYCLE
S4
3
/t
H4
2
+
timing
1
16
0
™