km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 21

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
Precharge Mechanisms
Figure 13 shows an example of precharge with the ROWR
packet mechanism. The PRER command must occur a time
Figure 14 (top) shows an example of precharge with a RDA
command. A bank is activated with an ROWA packet on the
ROW pins. Then, a series of four dualocts are read with RD
commands in COLC packets on the COL pins. The fourth of
these commands is a RDA, which causes the bank to auto-
matically precharge when the final read has finished. The
timing of this automatic precharge is equivalent to a PRER
command in an ROWR packet on the ROW pins that is
offset a time t
command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but
offset) PRER command in an ROWR packet when analyzing
interactions with other packets.
Figure 14 (middle) shows an example of precharge with a
WRA command. As in the RDA example, a bank is acti-
vated with an ROWA packet on the ROW pins. Then, two
dualocts are written with WR commands in COLC packets
on the COL pins. The second of these commands is a WRA,
which causes the bank to automatically precharge when the
final write has been retired. The timing of this automatic
precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time t
COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC
packet as well as a simultaneous (but offset) PRER
command in an ROWR packet when analyzing interactions
with other packets. Note that the automatic retire is triggered
by a COLC packet a time t
COL4
CTM/CFM
DQA8..0
ROW2
DQB8..0
..COL0
..ROW0
OFFP
T
0
ACT a0
T
1
from the COLC packet with the RDA
T
2
T
3
T
4
RTR
T
5
T
Figure 13: Precharge via PRER Command in ROWR Packet
6
t
after the COLC packet with
T
t
RAS
7
RC
T
8
T
9
T
10
T
11
T
12
T
OFFP
13
T
14
T
15
from the
T
16
T
17
T
18
T
19
Page 18
T
20
T
21
t
ACT command. This timing will serve as a baseline against
which the other precharge mechanisms can be compared.
the WR command unless the second COLC contains a RD
command to the same device. This is described in more
detail in Figure 17.
Figure 14 (bottom) shows an example of precharge with a
PREX command in an COLX packet. A bank is activated
with an ROWA packet on the ROW pins. Then, a series of
four dualocts are read with RD commands in COLC packets
on the COL pins. The fourth of these COLC packets
includes an COLX packet with a PREX command. This
causes the bank to precharge with timing equivalent to a
PRER command in an ROWR packet on the ROW pins that
is offset a time t
command.
T
RAS
22
T
23
T
after the ACT command, and a time t
PRER a5
24
T
25
T
26
T
27
T
28
T
OFFP
29
T
30
T
t
31
RP
from the COLX packet with the PREX
T
32
ACT b0
T
33
T
34
T
Rev. 1.01 Oct. 1999
35
Direct RDRAM
T
36
T
37
T
38
T
39
T
40
RP
b0 = {Da,Ba,Rb}
T
a0 = {Da,Ba,Ra}
41
a5 = {Da,Ba}
before the next
T
42
T
43
T
44
T
45
T
46
T
47
™