km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 44

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
t
COL4
t
CTM/CFM
CTM/CFM
DQA8..0
SCK
CMD
Power
a
b
ROW2
DQB8..0
ROW2
NU1
NU0
SIO0
SIO1
State
..COL0
Use 0 for NAP exit, 1 for PDN exit
Device selection timing slot is selected by DQS field of NAPX register
..ROW0
..ROW0
SCK
CMD
= 23•t
= 8•t
= 5•t
CYCLE
CYCLE
CYCLE
T
T
- (0.5•t
+ (2+NAPX)•t
The packet is repeated
0
0
from SIO0 to SIO1
T
T
1
1
NAP/PDN
Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
T
T
2
2
SCYCLE
t
T
T
CE
no entry to NAP or PDN
3
3
If PSX=1 in Init register, then
NAP/PDN exit is broadcast
(no PDEV field).
T
T
0/1
0/1
NAP exit
4
4
0
0
T
T
t
a
a
5
PDEV5..0
5
SCYCLE
)
S3
T
T
6
6
1
1
T
T
t
DQS=0
7
7
DQS=0
H3
t
T
T
b
NU0
if NSR=0
if NSR=1
8
8
T
T
t
PDEV5..0
9
9
S3
b,c
T
T
b
10
10
T
T
t
11
11
DQS=1
H3
DQS=1
T
T
b
12
12
NAP entry
T
T
13
13
Figure 48: NAP and PDN Exit
NAPR
T
Effective hold becomes
t
if [PDNX • 256 • t
T
b
b
H4
14
14
no exit
T
’=t
T
t
(
15
15
NAPX)•t
NU1
T
H4
T
16
16
+[PDNXA • 64 • t
T
T
17
17
T
T
18
18
SCYCLE
0
T
T
19
19
Page 41
No ROW packets may
overlap the restricted interval
No COL packets may
overlap the restricted interval
if device PDEV is exiting the
NAP-A or PDN-A states
SCYCLE
T
T
20
20
1
T
T
CTM/CFM
21
21
ROW2
)/(
T
T
..ROW0
SCK
CMD
] < [PDNXA • 64 • t
22
SCYCLE
22
256•PDNX•t
T
T
23
23
T
d
24
c
+t
Exit to STBY or ATTN depends upon whether RLXR was
asserted at NAP or PDN entry time
T
The DQS field must be written with “1” for this RDRAM.
25
PDNXB,MAX
T
26
T
STBY/ATTN
27
T
SCYCLE
T
0
28
T
SCYCLE
1
T
29
]-[PDNX • 256 • t
T
t
t
PU0
PU1
2
T
30
)
T
no entry to NAP or PDN
3
T
+t
31
= 5 • t
= 8 • t
T
= 23 • t
PDN exit
PDNXB,MAX
4
T
0
32
T
5
T
33
d
T
CYCLE
CYCLE
6
T
1
CYCLE
34
T
7
T
SCYCLE
Rev. 1.01 Oct. 1999
35
t
Direct RDRAM
T
].
PU0
T
8
ROP
COP
XOP
+ (2+256 • PDNX) • t
- (0.5 • t
36
T
9
T
37
]
T
10
T
38
T
11
T
SCYCLE
t
t
39
T
restricted
restricted
S4
S4
12
T
PDN entry
40
T
13
T
t
t
PDNR
41
T
H4
H4
14
T
no exit
)
t
42
T
PU1
15
T
43
T
T
16
ROP
SCYCLE
COP
XOP
44
T
if PSR=0
if PSR=1
17
T
45
T
18
T
46
0
T
19
T
47
T
™
20
1
T
21