ak5367a AKM Semiconductor, Inc., ak5367a Datasheet - Page 10

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ak5367a

Manufacturer Part Number
ak5367a
Description
96khz 24-bit ?? Adc With 0v Bias Selector
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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(Ta=-20°C ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V; C
Parameter
Master Clock Timing
LRCK Frequency
Audio Interface Timing
Control Interface Timing (I
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held long enough to bridge the 300ns-transition time of SCL.
MS0967-E-00
512fs, 256fs Frequency
768fs, 384fs Frequency
Pulse Width Low
Pulse Width Low
Pulse Width High
Pulse Width High
Duty Cycle
Slave mode
BICK Period
BICK Pulse Width Low
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
LRCK to SDTO (MSB) (Except I
BICK “↓” to SDTO
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Capacitive load on bus
Pulse Width High
Suppressed by Input Filter
(prior to first clock pulse)
Slave mode
Master mode
2
C Bus mode):
SWITCHING CHARACTERISTICS
2
S mode)
(Note
(Note
(Note
15)
14)
14)
tHD:DAT
tHD:STA
tSU:DAT
tSU:STA
tSU:STO
Symbol
tCLKH
tCLKH
tMSLR
tCLKL
tCLKL
tSCKH
tSCKL
tLRSH
tSHLR
tHIGH
tLOW
dSCK
fCLK
fCLK
tSCK
fSCK
tBUF
tLRS
tSSD
tSSD
fSCL
- 10 -
tSP
Cb
tR
tF
fs
12.288
8.192
10.5
10.5
min
L
−20
−20
160
1.3
0.6
1.3
0.6
0.6
0.1
0.6
16
16
32
45
65
65
30
30
=20pF)
0
0
-
-
-
-
64fs
typ
50
50
24.576
36.864
max
400
400
0.3
0.3
96
55
35
35
20
35
50
-
-
-
-
-
-
-
-
[AK5367A]
Units
MHz
MHz
2008/05
kHz
kHz
Hz
pF
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
%
%
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns

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