ak5367a AKM Semiconductor, Inc., ak5367a Datasheet - Page 16

• Manufacturer Part Number: ak5367a
• Description: 96khz 24-bit ?? Adc With 0v Bias Selector
• Manufacturer: AKM Semiconductor, Inc.

■
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
■
The AK5367A is placed in the power-down mode by bringing the PDN pin = “L” and the digital filter is also reset at the
same time. This reset must always be executed after power-up. At the power-down mode, the VCOM voltage is VSS1.
After exiting the power-down mode, the Charge pump circuit is powered up, then Pre-Amp circuit is automatically
powered up and an analog initialization cycle
4388 x LRCK cycles at slave mode, and 4385 x LRCK cycles in master mode. In the initialization, the both channel of
ADC output is “0” of 2’s complement. After the initialization, the ADC output is settled equal to analog input signal.(the
setting time is long as group delay)
Notes:
MS0967-E-00
(1) 4388/fs at slave mode, 4385/fs at master mode.
(2) Analog output corresponding to digital input has group delay (GD).
(3) ADC output is “0” data at the power-down mode.
(4) Place the AK5367A in power-down mode if MCLK, BICK and LRCK are not present.
(5) Power-up time of Charge Pump Circuit. 260/fs (slave mode), 257/fs (master mode).
Digital High Pass Filter
Power-down
Power Supply
(AVDD, DVDD, CVDD)
Charge Pump
Internal State
CVEE Pin
ADC
Internal State
Pre-amp In
ADC OUT
Clock In
MCLK,LRCK,BICK
PDN
(Analog)
(Digital)
Power-down
Power-down
(3)
0V
power-up
power-up
(5)
“0”data
Initialize
(1)
-CVDD
Figure 10. Power-down/up sequence example
starts(Figure
Idle Noise
GD
(2)
Normal Operation
Normal Operation
- 16 -
10). Therefore, the output data SDTO becomes available after
Idle Noise
GD
(2)
Power-down
(4)
Power-down
“0”data
(3)
0V
power-up
power-up
(5)
Initialize
-CVDD
(1)
Normal Operation
Idle Noise
Normal Operation
[AK5367A]
GD
(2)
2008/05