ak5367a AKM Semiconductor, Inc., ak5367a Datasheet - Page 21

• Manufacturer Part Number: ak5367a
• Description: 96khz 24-bit ?? Adc With 0v Bias Selector
• Manufacturer: AKM Semiconductor, Inc.

■
The AK5367A supports the first-mode I
The pull-up resistance of SDA,SCL pins should be connected below the voltage of DVDD+0.3V.
1. WRITE Operations
Figure 15
HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition
condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).
The most significant 7 bits of the slave address are fixed as “0110001”. If the slave address matches that of the AK5367A,
the AK5367A generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
R/W bit value of “1” indicates that the read operation is to be executed. “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK5367A. The format is MSB first, and those most
significant 6-bits are fixed to zeros
first, 8bits
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition
The AK5367A can perform more than one byte write operation per sequence. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal
2-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 02H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW
conditions.
MS0967-E-00
Serial Control Interface
shows the data transfer sequence for the I
(Figure
SDA
18). The AK5367A generates an acknowledge after each byte is received. A data transfer is always
S
T
A
R
T
S
Slave
Address
D7
0
0
R/W="0"
Figure 15. Data Transfer Sequence at the I
C
A
K
(Figure
D6
1
0
(Figure
Figure 18. Byte Structure after the second byte
Sub
Address(n)
2
C-bus system (max: 400kHz).
21).
17). The data after the second byte contains control data. The format is MSB
D5
1
0
Figure 17. The Second Byte
Figure 16. The First Byte
C
A
K
2
C-bus mode. All commands are preceded by START condition. A
Data(n)
D4
0
0
- 21 -
A
C
K
D3
0
0
(Figure
Data(n+1)
2
D2
C-Bus Mode
0
0
23) except for the START and STOP
C
A
K
A1
D1
1
C
A
K
(Figure
Data(n+x)
R/W
A0
D0
21). After the START
A
C
K
(Figure
S
T
O
P
P
[AK5367A]
2008/05
22). A