wm8770 Wolfson Microelectronics plc, wm8770 Datasheet - Page 20

• Manufacturer Part Number: wm8770
• Description: 24-bit, 192khz 8-channel Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8770
POWERDOWN MODES
DIGITAL AUDIO INTERFACE
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The WM8770 has powerdown control bits allowing specific parts of the WM8770 to be powered off
when not being used. The 8-channel input source selector and input buffer may be powered down
using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN8L/R)
are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input
PGAs.The four stereo DACs each have a separate powerdown control bit, DACPD[3:0] allowing
individual steteo DACs to be powered off when not in use. The analogue output mixers and EVRs
may also be powered down by setting OUTPD[3:0]. OUTPD[3:0] also switches the analogue outputs
VOUTL/R to VMIDDAC to maintain a dc level on the output. Setting AINPD, ADCPD, DACPD[3:0]
and OUTPD[3:0] will powerdown everything except the references VMIDADC, ADCREF and
VMIDDAC. These may be powered down by setting PDWN. Setting PDWN will override all other
powerdown control bits. It is recommended that the 8-channel input mux and buffer, ADC, DAC and
output mixers and EVRs are powered down before setting PDWN. The default is for all powerdown
bits to be set except PDWN.
The Powerdown control bits allow parts of the device to be powered down when not in use. For
example, if only an analogue bypass path from AINL/R to VOUTL/R is required the ADCPD and
DACPD[3:0] control bits may be set leaving the analogue input and analogue output powered up.
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In
both Master and Slave modes DACDAT is always an input to the WM8770 and ADCDAT is always
an output. The default is Slave mode.
In Slave mode (MS=0) ADCLRC, DACLRC and BCLK are inputs to the WM8770 (Figure 12).
DIN1/2/3/4, ADCLRC and DACLRC are sampled by the WM8770 on the rising edge of BCLK. ADC
data is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the
polarity of BCLK may be reversed so that DIN1/2/3/4, ADCLRC and DACLRC are sampled on the
falling edge of BCLK and DOUT changes on the rising edge of BCLK.
Figure 12 Slave Mode
MASTER AND SLAVE MODES
WM8770
CODEC
DIN1/2/3/4
ADCLRC
DACLRC
DOUT
BCLK
4
ENCODER/
DECODER
DSP
PD Rev 4.2 March 2008
Production Data
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