wm8770 Wolfson Microelectronics plc, wm8770 Datasheet - Page 32

• Manufacturer Part Number: wm8770
• Description: 24-bit, 192khz 8-channel Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8770
Table 10 Attenuation Register Map
w
00110
Analogue
Attenuation
DACL4
00111
Analogue
Attenuation
DACR4
01000
Master
Analogue
Attenuation
(all channels)
REGISTER
ADDRESS
BIT
6:0
6:0
6:0
7
8
7
8
7
8
MASTA[6:0]
UPDATE
R4ZCEN
UPDATE
UPDATE
L4ZCEN
R4A[6:0]
L4A[6:0]
MZCEN
Each DAC channel volume can be controlled digitally in an analogue volume stage after the DAC.
Attenuation is 0dB by default but can be set between 0 and –100dB in 1dB steps using the 7
Attenuation control words. All attenuation registers are double latched allowing new values to be pre-
latched to several channels before being updated synchronously. Setting the UPDATE bit on any
attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A
master attenuation register is also included, allowing all volume levels to be set to the same value in
a single write.
Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-
latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from
the next input sample. Writing to MASTA[6:0] overwrites any values previously sent to L1A[6:0],
L2A[6:0], L3A[6:0], L4A[6:0], R1A[6:0], R2A[6:0], R3A[6:0], R4A[6:0].
In addition a zero cross detect circuit is provided for each DAC volume under the control of bit 7
(xZCEN) in each DAC attenuation register. When ZCEN is set the attenuation values are only
updated when the input signal to the gain stage is close to the analogue ground level. This minimises
audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which
will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of
12.288MHz). The timeout clock may be disabled by setting TOD.
LABEL
10011
Timeout Clock Disable
REGISTER ADDRESS
Not latched
Not latched
Not latched
DEFAULT
1111111
1111111
1111111
(0dB)
(0dB)
(0dB)
0
0
0
3
BIT
Attenuation data for Left channel DACL4 in 1dB steps. See Table 11
DACL4 zero cross detect enable
Controls simultaneous update of all Attenuation Latches
Attenuation data for Right channel DACL4 in 1dB steps. See Table
11
DACR4 zero cross detect enable
Controls simultaneous update of all Attenuation Latches
Attenuation data for all channel DAC in 1dB steps. See Table 11
Master zero cross detect enable
Controls simultaneous update of all Attenuation Latches
0: Store L4A in intermediate latch (no change to output)
1: Store L4A and update attenuation on all channels.
0: Store R4A in intermediate latch (no change to output)
1: Store R4A and update attenuation on all channels.
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels.
LABEL
0: zero cross disabled
1: zero cross enabled
0: zero cross disabled
1: zero cross enabled
0: zero cross disabled
1: zero cross enabled
TOD
DEFAULT
0
DESCRIPTION
DAC Analogue Zero cross detect
timeout disable
DESCRIPTION
0 : Timeout enabled
1: Timeout disabled
PD Rev 4.2 March 2008
Production Data
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