wm8770 Wolfson Microelectronics plc, wm8770 Datasheet - Page 26

• Manufacturer Part Number: wm8770
• Description: 24-bit, 192khz 8-channel Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8770
CONTROL INTERFACE REGISTERS
w
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
The IWL[1:0] bits are used to control the input word length.
Note: If 32-bit mode is selected in right justified mode, the WM8770 defaults to 24 bits.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8770 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I
high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC channels.
Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC,
DACLRC and BCLK are outputs and are generated by the WM8770. In Slave mode ADCLRC,
DACLRC and BCLK are inputs to WM8770.
In left justified, right justified or I
ADCLRC/DACLRC. If this bit is set high, the expected polarity of ADCLRC/DACLRC will be the
opposite of that shown Figure 14, Figure 15 and Figure 16. Note that if this feature is used as a
means of swapping the left and right channels, a 1 sample phase difference will be introduced. In
DSP modes, the LRP register bit is used to select between early and late modes.
By default, ADCLRC/DACLRC and DIN1/2/3/4 are sampled on the rising edge of BCLK and should
ideally change on the falling edge. Data sources that change ADCLRC/DACLRC and DIN1/2/3/4 on
the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts
the polarity of BCLK to the inverse of that shown in Figure 14, Figure 15, Figure 16, Figure 17,
Figure 18, Figure 19 and Figure 20.
10110
Interface Control
10110
Interface Control
10110
Interface Control
10110
Interface Control
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
2
S mode, any width of 24 bits or less is supported provided that ADCLRC/DACLRC is
BIT
1:0
BIT
BIT
BIT
5:4
2
3
FMT[1:0]
WL[1:0]
LABEL
LABEL
LABEL
LABEL
BCP
LRP
2
S modes, the LRP register bit controls the polarity of
DEFAULT
DEFAULT
DEFAULT
DEFAULT
0
10
10
0
In left/right/I
ADCLRC/DACLRC Polarity (normal)
In DSP mode:
Interface format Select
BCLK Polarity (DSP modes)
Input Word Length
0 : normal ADCLRC/DACLRC
polarity
1: inverted ADCLRC/DACLRC
polarity
0 : Early DSP mode
1: Late DSP mode
00 : right justified mode
01: left justified mode
10: I
11: DSP (early or late) mode
0 : normal BCLK polarity
1: inverted BCLK polarity
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
2
DESCRIPTION
S mode
DESCRIPTION
DESCRIPTION
DESCRIPTION
2
S modes:
PD Rev 4.2 March 2008
Production Data
26