wm8770 Wolfson Microelectronics plc, wm8770 Datasheet - Page 36

• Manufacturer Part Number: wm8770
• Description: 24-bit, 192khz 8-channel Codec With Volume Control
• Manufacturer: Wolfson Microelectronics plc

WM8770
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ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled
using software control bit ADCHPD.
Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default
is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel
mux inputs are switched to buffered VMIDADC.
Table 14 ADC Input Mux Control
OUTPUT SELECT AND ENABLE CONTROL
Register bits MX1 to MX4 control the output select. The output select block consists of a summing
stage and an input select switch for each input allowing each signal to be output individually or
summed with other signals and output on each analogue output. The default for all outputs is DAC
playback only. VOUT1/2/3 may be selected to output DAC playback, AUX, analogue bypass or a
sum of these using the output select controls MX1/2/3[2:0]. VOUT4 may be selected to output DAC
playback, analogue bypass or a sum of these signals using MX4[1:0]. It is recommended that bypass
is not selected for output on more than two stereo channels simultaneously to avoid overloading the
input buffer, resulting in a decrease in performance.
The output mixers and EVRs can be powered down under control of OUTPD[3:0]. Each stereo
channel may be powered down separately. Setting OUTPD[3:0] will power off the mixer and EVR and
switch the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output.
When setting OUTPD MX1/2/3/4 should be set to deselect all signals.
ADC INPUT MUX AND POWERDOWN CONTROL
11011
ADC Mux and
Powerdown
Control
10110
ADC control
REGISTER ADDRESS
LMX[2:0]
000
001
010
011
100
101
110
111
REGISTER
ADDRESS
LEFT ADC INPUT
AIN1L
AIN2L
AIN3L
AIN4L
AIN5L
AIN6L
AIN7L
AIN8L
BIT
BIT
2:0
6:4
8
8
ADCHPD
LABEL
RMX[2:0]
LMX[2:0]
LABEL
AINPD
RMX[2:0]
000
001
010
011
100
101
110
111
DEFAULT
DEFAULT
RIGHT ADC INPUT
000
000
0
1
AIN1R
AIN2R
AIN3R
AIN4R
AIN5R
AIN6R
AIN7R
AIN8R
ADC Highpass filter disable:
ADC left channel input mux control
bits (see Table 14)
ADC right channel input mux
control bits (see Table 14)
Input mux and buffer powerdown
0: Highpass filter enabled
1: Highpass filter disabled
DESCRIPTION
DESCRIPTION
0: Input mux and buffer
enabled
1: Input mux and buffer
powered down
PD Rev 4.2 March 2008
Production Data
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