wm8770 Wolfson Microelectronics plc, wm8770 Datasheet - Page 9

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wm8770

Manufacturer Part Number
wm8770
Description
24-bit, 192khz 8-channel Codec With Volume Control
Manufacturer
Wolfson Microelectronics plc
Datasheet

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Figure 1 Master Clock Timing Requirements
Table 1 Master Clock Timing Requirements
Note: If MCLK period is longer than maximum specified above, DACs are powered down with internal digital audio filters
being reset. In this mode, all registers will retain their values and can be accessed in the normal manner through the
control interface. Once MCLK is restored, the DACs are automatically powered up.
DIGITAL AUDIO INTERFACE – MASTER MODE
Figure 2 Audio Interface - Master Mode
w
MASTER CLOCK TIMING
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T
otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
Power-saving mode activated
Normal mode resumed
WM8770
CODEC
MCLK
DIN1/2/3/4
ADCLRC
DACLRC
DOUT
BCLK
4
SYMBOL
t
t
t
MCLKH
MCLKY
MCLKL
t
MCLKL
t
MCLKY
ENCODER/
DECODER
DSP/
A
t
MCLKH
After MCLK re-started
After MCLK stopped
TEST CONDITIONS
= +25
o
C, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless
40:60
MIN
0.5
11
11
28
2
TYP
PD Rev 4.2 March 2008
60:40
1000
MAX
10
1
WM8770
MCLK
cycle
UNIT
ns
ns
ns
µs
9

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