k9f1608w0a-tcb0 Samsung Semiconductor, Inc., k9f1608w0a-tcb0 Datasheet - Page 21

• Manufacturer Part Number: k9f1608w0a-tcb0
• Description: 2m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9F1608W0A-TCB0, K9F1608W0A-TIB0
Figure 6. Sequential Row Read2 Operation
PAGE PROGRAM
The device is programmed basically on a page basis. But it also allows multiple partial page programming of a byte or consecutive
bytes up to 264 may be programmed in a single page program cycle. The number of partial page programming operation in the same
page without an intervening erase operation must not exceed ten. The addressing may be done in random order in a block. A page
program cycle consist of a serial data loading period in which up to 264 bytes of data must be loaded into the device, and nonvolatile
programming period in which the loaded data is programmed into the appropriate cell.
The sequential data loading period begins by inputting the Serial Data Input command(80H), followed by the three cycle address
input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.
In order to program the bytes in the spare columns of 256 to 263, the pointer should be set to the spare area by writing the Read 2
command(50H) to the command register. The pointer remains in the spare area unless the Read 1 command(00H) is entered to
retum to the main area. The Page Program confirm command(10H) initiates the programming process. Writing 10H alone without
perviously entering the serial data will not initiate the programming process. The internal write controller automatically executes the
algorithms and timings necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts,
the Status Register may be read RE and CE low after the Read Status command(70H) is written to it. The CPU can detect the com-
pletion of program cycle by monitoring the R/B output, or the Status bit(I/O
and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O
be checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The com-
mand register remains in Read Status command mode until another valid command is written to the command register.
R/B
I/O
Figure 7. Program & Read Status Operation
R/B
I/O
0
0 ~ 7
~
7
50H
80H
(A
Don't Care)
3
~ A
7
A
Start Add.(3Cycle)
:
0
~ A
A
Address & Data Input
0
264 Byte Data
~ A
2
& A
7
& A
8
~ A
8
~ A
20
t
R
20
Data Field
Data Output
10H
1st
21
Spare Field
6
t
R
) of the Status Register. Only the Read Status command
t
PROG
1st
2nd
Nth
Data Output
(8Byte)
2nd
70H
FLASH MEMORY
t
R
Fail
I/O
Data Output
0
(8Byte)
Nth
0
) may
Pass