k9f1608w0a-tcb0 Samsung Semiconductor, Inc., k9f1608w0a-tcb0 Datasheet - Page 4

• Manufacturer Part Number: k9f1608w0a-tcb0
• Description: 2m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PRODUCT INTRODUCTION
K9F1608W0A-TCB0, K9F1608W0A-TIB0
The K9F1608W0A is a 16.5Mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. Spare eight columns are located
from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays accommodating data transfer
between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that
are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 16 pages
formed by one NAND structures, totaling 2,112 NAND structures of 16 cells. The array organization is shown in Figure 2. The pro-
gram and read operations are executed on a page basis, while the erase operation is executed on block basis. The memory array
consists of 512 separately or grouped erasable 4K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
K9F1608W0A.
The K9F1608W0A has addresses multiplexed into 8 I/O s. This scheme dramatically reduces pin counts and allows systems
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O`s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle
except for Block Erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block
address loading. The 2M byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : col-
umn address, low row address and high row address, in that order. Page Read and Page Program need the same three address
cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F1608W0A.
Table 1. COMMAND SETS
Sequential Data Input
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Read Status
Function
1st. Cycle
FFh
80h
00h
50h
90h
10h
60h
70h
2nd. Cycle
D0h
-
-
-
-
-
-
-
4
Acceptable Command during Busy
O
O
FLASH MEMORY