ppc405exr Applied Micro Circuits Corporation (AMCC), ppc405exr Datasheet
ppc405exr
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ppc405exr Summary of contents
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PowerPC 405EXr Embedded Processor Features ® • AMCC PowerPC 405 32-bit RISC processor core operating from 333MHz to 533MHz including 16KB I- and D-caches with parity checking • On-chip 128-bit processor local bus (PLB) operating up to 200MHz • ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PowerPC 405 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 USB 2.0 OTG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR1/2 SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PCI Express ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor List of Figures Figure 1. PPC405EXr Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Package 27mm, 388-Ball EPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3. Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 4. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 5. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 6. Input Setup and Hold Timing Waveform for RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 7 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor List of Tables Table 1. System Memory Address Map (4GB System Memory Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 5. Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6. Non-Functional Ball Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 7. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 9 ...
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... The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC405EXr Embedded Processor User’s Manual for details about accessing these registers. ...
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... Arbiter DDR1/2 EIP-94 SDRAM Security Controller Feature The PPC405EXr is designed using the IBM Microelectronics Blue Logic blocks are integrated together to create an ASIC (application-specific integrated circuit) product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect 6 DCRs IICx2/ SCP UART ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Address Maps The PPC405EXr incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EXr processor through the use of mtdcr and mfdcr instructions ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 2. DCR Address Map Function 1 Total DCR Address Space Reserved CPR (Clocking Power-on Reset) System DCRs DDR 2/1 SDRAM Controller External Bus Controller (EBC) External Bus Master (EBM) Reserved PLB4XAHB Bridge Reserved PCI Express 0 Reserved PLB4 Arbiter ...
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... Selectable processor vs. bus clock ratios (N:1 ratio only, where N = Internal Buses The PPC405EXr contains four internal buses: the processor local bus (PLB), the Advanced High-Performance Bus (AHB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. High performance devices such as the processor, the DDR SDRAM memory controller, PCI Express, the Ethernet MAL, and DMA utilize the PLB ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor OPB The OPB provides 32-bit address and data interfaces, and operates up to 100MHz. There are bridges between the OPB and the PLB. Features include: • Pipelined read support • Dynamic bus sizing • Single-cycle data transfer between masters and slaves ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor independent set of registers needed for data transfer: a control register, a source address register, a destination address register, and a transfer count register. Features include: • Memory-to-memory transfers • Buffered memory-to-peripheral transfers • Buffered peripheral-to-memory transfers • ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor PCI Express The PCI Express single-lane interface include the following features: Features include: • Compliant with PCI Express base specification 1.1 • Port can be End Point or Root Complex. (Upstream & Downstream) • PCI-Express to PCI-Express opaque (Non-Transparent) bridge • ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor • Secure Real-Time Protocol (sRTP) features – Packet transforms – ROC removal and TAG insertion – Variable bypass offset of header length per packet • Media Access Control Security (MACSec) features – Cipher suite GCM-AES-128 – Header insertion and removal – ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor • Hold and shift registers (eliminate need for precise synchronization between processor and serial data in character mode) • Complete status reporting • Full prioritized interrupt system controls • Independently controlled transmit, receive, line status, and data set interrupts • ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor General Purpose I/O (GPIO) Controller The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by register bit settings controlled by software. This significantly reduces the number of package pins needed to support multiple I/O groups ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor • IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame transmitting) • Wake-on-LAN and Power-over-Internet supported • Programmable internal/external loopback capabilities • OPB slave (MAC) and PLB master (MAL) interfaces for control and configuration are 32 bits wide • ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Figure 2. Package 27mm, 388-Ball EPBGA Gold Gate Release Corresponds to A01 Ball Location Top View Epoxy Mold Compound Side View PCB Substrate Bottom View 27 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 2 of 14) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 EAGND EAV DD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EOV DD EOV DD EOV DD EOV DD EOV DD EOV DD [ExtAck]GPIO25[DMAAck3][IRQ3] [ExtReq]GPIO24[DMAEOT2][IRQ4] ExtReset AMCC Proprietary Revision 1 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 3 of 14) Signal Name GMCCD GMCCrS GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk GMCRxClk, GMC0RxClk GMCRxD0, GMC0RxD0 GMCRxD1, GMC0RxD1 GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4 GMCRxD5 GMCRxD6 GMCRxD7 GMCRxDV, GMC0RxCtl GMCRxEr GMCTxClk GMCTxD0, GMC0TxD0 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 4 of 14) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 5 of 14) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 6 of 14) Signal Name GPIO00[PerDataPar0] GPIO01[PerDataPar1] GPIO02[PerDataPar2] GPIO03[PerDataPar3] GPIO04[PerData20][USB2Data4] GPIO05[PerData21][USB2Data5] GPIO06[PerData22][USB2Data6] GPIO07[PerData23][USB2Data7] GPIO08[PerCS1][NFCE1][IRQ7] GPIO09[PerCS2][NFCE2][IRQ8] GPIO10[PerCS3][NFCE3][IRQ9] GPIO11[IRQ6] GPIO12[PerData16][USB2Data0] GPIO13[PerData17][USB2Data1] GPIO14[PerData18][USB2Data2] ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 7 of 14) Signal Name [IRQ0]GPIO31[DMAAck1] [IRQ1]GPIO30[DMAReq1] [IRQ2]GPIO29[DMAEOT1] [IRQ3][ExtAck]GPIO25[DMAAck3] [IRQ4][ExtReq]GPIO24[DMAEOT2] [IRQ5][BusReq]GPIO27[DMAEOT3] [IRQ6]GPIO11 [IRQ7][PerCS1][NFCE1]GPIO08 [IRQ8][PerCS2][NFCE2]GPIO09 [IRQ9][PerCS3][NFCE3]GPIO10 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 8 of 14) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 9 of 14) Signal Name [NFALE]PerData30 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO08[IRQ7] [NFCE2][PerCS2]GPIO09[IRQ8] [NFCE3][PerCS3]GPIO10[IRQ9] [NFCLE]PerData29 [NFData00]PerData00 [NFData01]PerData01 [NFData02]PerData02 [NFData03]PerData03 [NFData04]PerData04 [NFData05]PerData05 [NFData06]PerData06 [NFData07]PerData07 [NFData08]PerData08 [NFData09]PerData09 [NFData10]PerData10 [NFData11]PerData11 [NFData12]PerData12 [NFData13]PerData13 [NFData14]PerData14 [NFData15]PerData15 [NFRdyBusy]PerData31 [NFREn]PerData27 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 10 of 14) Signal Name PCIE0ATB PCIE0ClkC PCIE0ClkT PCIE0RExt PCIE0RExtG PCIE0Rx PCIE0Rx PCIE0Tx PCIE0Tx [PerAddr05]GPIO26[TS3][DMAEOT0] PerAddr06[TS2][DMAReq0] PerAddr07[TS1][DMAAck0] PerAddr08[TS0][DMAReq3] PerAddr09[TS1E] PerAddr10[TS0E] PerAddr11[TS1O] PerAddr12[TS0O] PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 11 of 14) Signal Name PerData00[NFData00] PerData01[NFData01] PerData02[NFData02] PerData03[NFData03] PerData04[NFData04] PerData05[NFData05] PerData06[NFData06] PerData07[NFData07] PerData08[NFData08] PerData09[NFData09] PerData10[NFData10] PerData11[NFData11] PerData12[NFData12] PerData13[NFData13] PerData14[NFData14] PerData15[NFData15] [PerData16]GPIO12[USB2Data0] [PerData17]GPIO13[USB2Data1] [PerData18]GPIO14[USB2Data2] [PerData19]GPIO15[USB2Data3] [PerData20]GPIO04[USB2Data4] [PerData21]GPIO05[USB2Data5] [PerData22]GPIO06[USB2Data6] [PerData23]GPIO07[USB2Data7] PerData24[USB2Dir] PerData25[USB2Stop] PerData26[USB2Next] ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 12 of 14) Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAGND SAV DD SCPClkOut[IIC1SClk] SCPDI SCPDO[IIC1SData VREF ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 13 of 14) Signal Name [TS0E]PerAddr10 [TS0O]PerAddr12 [TS1E]PerAddr09 [TS1O]PerAddr11 [UART0CTS]GPIO18 [UART0DCD][UART1CTS]GPIO16 [UART0DSR][UART1RTS]GPIO17 [UART0DTR][UART1Tx]GPIO20 [UART0RI][UART1Rx]GPIO21 [UART0RTS]GPIO19 UART0Rx UART0Tx [UART1CTS][UART0DCD]GPIO16 [UART1RTS][UART0DSR]GPIO17 [UART1Rx][UART0RI]GPIO21 [UART1Tx][UART0DTR]GPIO20 UARTSerClk USB2Clk [USB2Data0][PerData16]GPIO12 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 14 of 14) Signal Name AMCC Proprietary Revision 1.10 - July 10, 2008 Preliminary Data Sheet Ball Interface Group ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor In the following table, only the default signal name is shown for each ball. Shared balls are marked with an asterisk (*). To determine what signals or functions are shared on those balls, look up the default signal name in “Signals Listed Alphabetically” on page 18. The following table lists the signals by ball assignment. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball E01 GND F01 E02 UARTSerClk F02 E03 GND F03 OV E04 F04 DD E05 No ball F05 E06 No ball F06 E07 No ball F07 E08 No ball F08 E09 No ball F09 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball J01 PCIE0Rx K01 J02 PCIE0Rx K02 AV J03 K03 DD J04 GND K04 J05 No ball K05 J06 No ball K06 J07 No ball K07 J08 No ball K08 J09 No ball K09 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball N01 Reserved P01 N02 Reserved P02 AV N03 P03 DD AV N04 P04 DD N05 No ball P05 N06 No ball P06 N07 No ball P07 N08 No ball P08 N09 No ball P09 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball U01 GND V01 U02 GND V02 U03 GPIO28 V03 V U04 V04 DD U05 No ball V05 U06 No ball V06 U07 No ball V07 U08 No ball V08 U09 No ball V09 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball AA01 IIC0SData AB01 AA02 IIC1SClk * AB02 AA03 SCPDI AB03 AA04 IIC1SData * AB04 AA05 No ball AB05 AA06 No ball AB06 AA07 No ball AB07 AA08 No ball AB08 AA09 No ball ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball AE01 GMCTxD0 * AF01 AE02 GND AF02 AE03 GMCMDClk AF03 AE04 GMCGTxClk * AF04 AE05 GMCRxDV * AF05 AE06 GMCRxD7 AF06 AE07 EAGND AF07 EAV AE08 AF08 DD AE09 GMCRxD4 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Pin Group List The following table provides a summary of the number of package pins (balls) associated with each functional interface group. Table 5. Pin Groups Total Signal Pins Total Power Pins In the table “Signal Functional Description” on page 41, each external signal is listed along with a short description of the signal function. Active-low signals (for example, Halt) are marked with an overline. See the preceding table, “ ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Reserved Balls The balls marked Reserved on this chip are not functional. However, most of the reserved balls cannot be left unconnected. Connect the balls shown in the following table as indicated: 40 Table 6. Non-Functional Ball Connections Ball Connection N01 GND ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Signal Functional Descriptions The following table provides a description of the I/O signals on the PPC405EXr. Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. ...
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... Signal Name System Interface SysClk System input clock. SysErr Machine check exception has occurred. Main system reset. This signal may be driven by the PPC405EXr to SysReset cause a board level reset to occur. TestEn Test enable. Reserved for manufacturing LSSD test. Halt External request to stop the processor. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 7. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 39 for recommended termination values. ...
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... Case Temperature Range under bias Junction Temperature Range Notes: 1. The analog voltages can be derived from the +1.2V and +2.5V supplies, but must be filtered as shown below before entering the PPC405EXr. Use a separate filter for each voltage. This circuit can be used for GND 2. The device meets all electrical specifications at a junction temperature, under bias, of 125º ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 9. Package Thermal Specifications The PPC405EXr is designed to operate within a case temperature range Conditions” on page 50. Thermal resistance values for the EPBGA packages in a convection environment are as follows: Parameter Symbol Junction-to-ambient θ thermal resistance JA without heat sink Junction-to-ambient θ ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 10. Recommended DC Operating Conditions (Sheet Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage—333MHz & 400MHz Logic Supply Voltage—533MHz ...
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... A 533MHz part running at 400MHz or less can operate case temperature of +95°C. Power Supply Sequence All the PPC405EXr I/O designs are power supply sequence independent. There is no requirement that the power supplies power up in any particular order. The following items are power sequence considerations: • ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 11. I/O Input Capacitance Parameter 3.3V LVTTL 2.5V CMOS 2.5/1.8V SSTL2 PCI Express differential data receiver PCI Express differential data transmitter PCI Express differential clock receiver Table 12. Typical DC Power Supply Requirements with DDR1 SDRAM +1.2V nom (V + Frequency (MHz) +1 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 14. Typical DC Power Supply Requirements with DDR2 SDRAM +1.2V nom (V + Frequency (MHz) +1.15V +1.25V 333 0.97 na 400 1.09 na 533 na 1.46 Notes: 1. Typical power is measured on a typical process part at a case temperature of +85°C at the specified voltages while running Linux and test applications that exercise each function with representative traffic (PCI Express, Gigabit Ethernet, USB, and Security) ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 16. DC Power Supply Loads with DDR1 SDRAM Parameter V (+1.2V) active operating current DD AV (+1.2V) active operating current DD AHV (+2.5V) active operating current DD OV (+3.3V) active operating current DD + EOV SV (+2.5V) active operating current DD DD SAV (+2.5V) active operating current DD EAV (+2.5V) active operating current ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Power Control This chip has power management control to put the following functional units to sleep if not needed. The typical and maximum power consumption for the each of these units is: Table 18. Power Contribution of Functional Units Functional Unit EBM/OPB ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Spread Spectrum Clocking Care must be taken if using a spread spectrum clock generator (SSCG) with the PPC405EXr. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is called tracking skew ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 20. Peripheral Interface I/O Clock Timings (not SDRAM or PCI-E) Clock GMCTxClk frequency GMCTxClk high time GMCTxClk low time GMCRxClk frequency GMCRxClk high time GMCRxClk low time GMCGTxClk GMCMDClk GMCRefClk GMCRefClk edge stability (phase jitter, cycle-to-cycle) ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Figure 4. Input Setup and Hold Timing Waveform System Clock 1.5V Inputs 1.5V Figure 5. Output Delay and Float Timing Waveform System Clock 1. MAX Outputs 1. MIN Outputs 1. MIN MIN Valid Valid MAX Revision 1.10 - July 10, 2008 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Figure 6. Input Setup and Hold Timing Waveform for RGMII Signals GMCnRxClk 1.25V Inputs 1.25V RGMII 1000Mbps timing is with reference to the raising and falling edge of GMCnRxClk. RGMII 10/100Mbps timing is with reference only to the raising edge of GMCnRxClk. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 21. I/O Specifications Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min Ethernet GMII Interface GMCMDIO na GMCCD 2 GMCCrS 2 GMCRxD0:7 1.85 GMCRxDV 1.95 GMCRxEr 1.95 GMCTxD0:7 GMCTxEr GMCTxEn Ethernet RGMII Interface ( GMCnRxD0:3 0 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 21. I/O Specifications Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time Hold Time (T min System Interface GPIO00:10 na GPIO11:15 na GPIO16:27 na GPIO28 na GPIO29:31 na Halt na SysErr na SysReset na External Peripheral Interface PerAddr05:31 1.8 PerCS0:3 PerData00:31 2 ...
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... In a typical system, users advance MemClkOut by 90°. This depends on the specific application and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM Controller chapter in the PPC405EXr Embedded Processor User’s Manual). The signals are terminated as indicated in Figure 8 for the DDR timing data and output currents in the following sections ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 22. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:31 ECC0:7 DM0:4 MemClkOut0 MemAddr00:14 BA0:2 RAS CAS WE BankSel0:1 MemClkEn DQS0:4 MemODT0:1 DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes as indicated in Figure 9. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 9. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut0 Addr/Cmd DQS MemData T = Setup time for address and command signals to MemClkOut0 Hold time for address and command signals from MemClkOut0 ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 25. I/O Timing—DDR SDRAM T Signal Name MemAddr00:14 BA0:2 BankSel0:1 MemClkEn CAS RAS WE Table 26. I/O Timing—DDR SDRAM Write Timing T Notes and T are measured under worst case conditions Clock speed for the values in the table is 200MHz. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor The feedback signal to the Feedback Data Capture Window is adjusted for propagation delay by the fine/coarse delays and is automatically adjusted for variations in the DDR I/O due to supply voltage and temperature. Compensation for driver/receiver variations is accomplished by driving and receiving the feedback signal on the external MemFBD and MemFBR pins ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Figure 10. DDR SDRAM Read Data Path for a Single Data Bit Ext FeedBack Signals Driver MemFBD Coarse Delay Rec Fine Delay MemFBR DQS aligned Feedback Data Capture Window Package pins FF Mux DQS Rising MemData ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Figure 11. DDR SDRAM Memory Data and DQS DQS MemData Table 27. I/O Timing—DDR SDRAM Read Timing and T are measured under worst case conditions Clock speed for the values in the table is 200MHz. 3. The time values in the table include 1 cycle at 200MHz (5ns x 0.25 = 1.25 ns). ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Figure 12. DDR SDRAM Read Cycle Timing—Example DDR 1X Clock DDR 2X Clock MemClkOut0 (Diff.) DQS at Pin Data at Pin MemFBR at Pin DDR 1X Clock cycle Delayed DQS Data Out Stage 1 (0) Data Out Stage 1 (1) Data out Stage 1 (2) ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor PCI Express (PCI-E) I/O Specifications The following tables provide the required I/O timing information regarding the use of the PCI Express interface on this chip. Table 28. PCI-E Receiver I/O Specifications Parameter Unit Interval (UI) Differential Rx peak-peak voltage Receiver eye time opening ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Table 30. PCI-E Transmitter I/O Specifications Parameter Unit Interval (UI) Differential p-p Tx voltage swing Low power differential p-p Tx voltage swing Tx de-emphasis level ratio Minimum Tx eye width Maximum time between the jitter median and maximum deviation from the median Transmitter rise and fall time ...
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... EBC 8-bit wide NAND Flash IIC ROM at address 0xA8 EBC 8-bit wide ROM IIC ROM at address 0xA4 Note: See the PPC405EXr Embedded Processor User’s Manual for option descriptions and other details regarding the boot process. 72 Revision 1.10 - July 10, 2008 Preliminary Data Sheet ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor Revision Log Date Version 06/07/2007 1.00 06/28/2007 1.01 10/25/2007 1.02 11/21/2007 1.03 01/04/2008 1.04 01/15/2008 1.05 01/16/2008 1.06 02/13/2008 1.07 02/15/2008 1.08 05/02/2008 1.09 07/10/2008 1.10 AMCC Proprietary Contents of Modification Initial creation of document. Updates and corrections. Correct AMCC phone numbers. Change PerErr to always pull down. Add revised I/O timing figures from 405EX DS. ...
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... PPC405EXr – PowerPC 405EXr Embedded Processor 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’ ...