ppc405exr Applied Micro Circuits Corporation (AMCC), ppc405exr Datasheet - Page 68
ppc405exr
Manufacturer Part Number
ppc405exr
Description
Powerpc 405exr Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet
1.PPC405EXR.pdf
(74 pages)
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PPC405EXr – PowerPC 405EXr Embedded Processor
Figure 11. DDR SDRAM Memory Data and DQS
Table 27. I/O Timing—DDR SDRAM Read Timing T
1. T
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted T
of the cycle time for the lower clock frequency (e.g., T
In the following example, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight
skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the DQS signals be matched.
The following example shows the timing relationship between SDRAM DDR Data at the input pin and storing the
data in Stage 1.
68
MemData00:07
MemData08:15
MemData16:23
MemData24:31
ECC0:7
SD
and T
Signal Names
HD
are measured under worst case conditions.
SD
and T
MemData
HD
DQS
values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
T
T
SD
HD
SD
- 1.25 + 0.25T
SD
and T
Read Data vs DQS Set up
HD
CYC
T
SD
0.27
0.27
0.27
0.27
0.27
).
(ns)
Preliminary Data Sheet
Revision 1.10 - July 10, 2008
Read Data vs DQS Hold
T
HD
0.45
0.45
0.45
0.45
0.45
(ns)
AMCC Proprietary