ppc405exr Applied Micro Circuits Corporation (AMCC), ppc405exr Datasheet - Page 65

• Manufacturer Part Number: ppc405exr
• Description: Powerpc 405exr Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PPC405EXr – PowerPC 405EXr Embedded Processor
Table 25. I/O Timing—DDR SDRAM T
Table 26. I/O Timing—DDR SDRAM Write Timing T
Notes:
1. T
2. Clock speed for the values in the table is 200MHz.
3. The time values in the table include 1/4 of a cycle at 200MHz (5ns x 0.25 = 1.25 ns).
4. To obtain adjusted T
DDR SDRAM Read Operation
Data on a read is edge aligned with DQS. To capture the incoming data on the rising and falling edges, DQS is
delayed by the DDR controller in order to center a DQS edge on valid data. Programmable registers control the
delay.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by memory layout and process, a three-stage data path is
used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
Figure 10 shows the data read path of a single data bit. Data entering on the left is captured in the Stage 1 Flip
Flops. Four Flip Flops are needed to capture an entire four beat burst on the DDR interface. The DDR controller
only supports burst of four. Data captured on the rising edge of DQS is stored in the even numbered Flip Flops.
Like wise, data captured on the falling edge of DQS is stored in the odd numbered Flips Flops.
To latch the data in Stage 1, a delayed version of DQS is used. Initialization software is responsible for tuning the
DQS delay timing so that DQS is centered on valid data. Since there is process variation between parts and
possible voltage variations on boards, read tuning is required. Fixed DQS delay values should not be used on
production systems.
The Feedback Data Capture Window selects which Flip Flop is used to store the data sampled by DQS. Each
output of this block generates a pulse to an input multiplexer. The series of four pulses selecting the input
multiplexer is initiated by a feedback signal pulse on the input of the Feedback Data Capture Window. The DDR
controller calculates when to assert the feedback signal based on when the data should be present after a read
command.
The width of the feedback pulse is the same as DDR 1X clock. The internal DDR 1X clock is the same frequency
as MemClkOut0. MemClkOut0 is slightly delayed relative to DDR 1X clock due to the insertion delay of the drivers.
AMCC Proprietary
MemAddr00:14
BA0:2
BankSel0:1
MemClkEn
CAS
RAS
WE
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
ECC0:7, DM4
of the cycle time for the lower clock frequency (for example, T
SD
and T
Signal Names
HD
Signal Name
are measured under worst case conditions.
SD
and T
HD
values for lower clock frequencies, subtract 1.25 ns from the values in the table and add 1/4
Reference Signal
SA
DQS0
DQS1
DQS2
DQS3
DQS4
and T
HA
T
SA
SD
(ns) Minimum
and T
1.08
1.12
1.09
1.10
1.10
1.09
1.08
SD
HD
− 1.25 + 0.25T
T
SD
1.067
1.074
1.082
1.088
1.012
(ns)
CYC
).
Preliminary Data Sheet
Revision 1.10 - July 10, 2008
T
HA
(ns Minimum)
1.12
1.15
1.13
1.16
1.13
1.12
1.16
T
HD
0.973
0.973
0.973
0.973
0.973
(ns)
65