s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 157

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
FORMAT 4: ALU OPERATIONS
OPERATION
The following instructions perform ALU operations on a Lo register pair.
All instructions in this group set the CPSR condition codes.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
OP
15
0
AND Rd, Rs
EOR Rd, Rs
LSL Rd, Rs
LSR Rd, Rs
ASR Rd, Rs
ADC Rd, Rs
SBC Rd, Rs
ROR Rd, Rs
TST Rd, Rs
NEG Rd, Rs
CMP Rd, Rs
CMN Rd, Rs
ORR Rd, Rs
MUL Rd, Rs
BIC Rd, Rs
MVN Rd, Rs
14
0
THUMB Assembler
13
0
12
0
Table 4-5. Summary of Format 4 Instructions
11
0
[2:0] Source/Destination Register
[5:3] Source Register 2
[9:6] Opcode
10
0
ANDS Rd, Rd, Rs
EORS Rd, Rd, Rs
MOVS Rd, Rd, LSL Rs
MOVS Rd, Rd, LSR Rs
MOVS Rd, Rd, ASR Rs
ADCS Rd, Rd, Rs
SBCS Rd, Rd, Rs
MOVS Rd, Rd, ROR Rs
TST Rd, Rs
RSBS Rd, Rs, #0
CMP Rd, Rs
CMN Rd, Rs
ORRS Rd, Rd, Rs
MULS Rd, Rs, Rd
BICS Rd, Rd, Rs
MVNS Rd, Rs
Figure 4-5. Format 4
9
ARM Equipment
NOTE
Op
6
5
Rd:= Rd AND Rs
Rd:= Rd EOR Rs
Rd := Rd << Rs
Rd := Rd >> Rs
Rd := Rd ASR Rs
Rd := Rd + Rs + C-bit
Rd := Rd - Rs - NOT C-bit
Rd := Rd ROR Rs
Set condition codes on Rd AND Rs
Rd = - Rs
Set condition codes on Rd - Rs
Set condition codes on Rd + Rs
Rd := Rd OR Rs
Rd := Rs * Rd
Rd := Rd AND NOT Rs
Rd := NOT Rs
Rs
3
THUMB INSTRUCTION SET
2
Action
Rd
0
4-11