s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 216

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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NAND FLASH CONTROLLER
SPECIAL FUNCTION REGISTERS
NAND FLASH CONFIGURATION (NFCONF) REGISTER
6-6
Enable/Disable
Reserved
Initialize ECC
NAND Flash Memory
chip enable
TACLS
Reserved
TWRPH0
Reserved
TWRPH1
Register
NFCONF
NFCONF
0x4E000000
Address
[14:13]
[10:8]
[6:4]
[2:0]
[15]
[12]
[11]
Bit
[7]
[3]
R/W
R/W
NAND flash controller enable/disable
0 = Disable NAND Flash Controller
1 = Enable NAND Flash Controller
After auto-boot, this bit is cleared to 0 automatically.
For the access to the NAND flash memory, this bit must
be set.
Reserved
Initialize ECC decoder/encoder
0 : Not initialize ECC
(S3C2410A supports only 512-Byte ECC checking, so it is
required to set ECC initialization per 512 Bytes.)
NAND flash memory nFCE control
0 : NAND flash nFCE = L (active)
1 : NAND flash nFCE = H (inactive)
(After auto-boot, nFCE will be inactive.)
CLE & ALE duration setting value (0~7)
Duration = HCLK * (TACLS + 1)
Reserved
TWRPH0 duration setting value (0~7)
Duration = HCLK * (TWRPH0 + 1)
Reserved
TWRPH1 duration setting value (0~7)
Duration = HCLK * (TWRPH1 + 1)
NAND flash configuration
Description
1 : Initialize ECC
Description
Reset Value
Initial State
S3C2410A
0
0
0
0
0

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