s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 214

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

NAND FLASH CONTROLLER
PIN CONFIGURATION
BOOT AND NAND FLASH CONFIGURATIONS
1. OM[1:0] = 00b : Enable NAND flash controller auto boot mode
2. NAND flash memory page size should be 512Bytes.
3. NCON : NAND flash memory address step selection
512-BYTE ECC PARITY CODE ASSIGNMENT TABLE
S3C2410A generates 512-Byte ECC Parity Code during Write/Read operation. ECC Parity Code consists of 3 Bytes
per 512-Byte data.
ECC generator block executes the followings:
1. When MCU writes data to NAND, the ECC generator block generates ECC code.
2. When MCU reads data from NAND, the ECC generator block generates ECC code and users compare it with
6-4
D[7:0]
CLE
ALE
nFCE
nFRE
nFWE
R/nB
0 : 3 Step addressing
1 : 4 Step addressing
pre-written ECC code.
ECC0
ECC1
ECC2
24-bit ECC Parity Code = 18-bit Line parity + 6-bit Column Parity
: Data/Command/Address In/Out Port (shared with the data bus)
: Command Latch Enable (Output)
: Address Latch Enable (Output)
: NAND Flash Write Enable (Output)
: NAND Flash Ready/nBusy (Input)
: NAND Flash Chip Enable (Output)
: NAND Flash Read Enable (Output)
DATA7
P1024
P64
P4
DATA6
P1024’
P64’
P4’
DATA5
P512
P32
P2
DATA4
P512’
P32’
P2’
DATA3
P256
P16
P1
DATA2
P256’
P16’
P1’
DATA1
P2048
P128
P8
S3C2410A
DATA0
P2048’
P128’
P8’