s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 591

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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ARM920T PROCESSOR
CLOCK MODES
Appendix 5
CLOCK MODES
OVERVIEW
The ARM920T has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK,
which can be seen on the CPCLK output as shown in Figure 5-1. GCLK can be sourced from either BCLK or FCLK
depending on the clocking mode, selected using nF bit and iA bit in CP15 register 1 (see Register 1: Control register
on page 2-10). The three clocking modes are FastBus, synchronous and asynchronous.
The ARM920T is a static design and both clocks can be stopped indefinitely without loss of state. From Figure 5-1
it can be seen that some of the ARM920T macrocell signals will have timing specified with relation to GCLK, which
can be either FCLK or BCLK depending on the clocking mode
BCLK
CPCLK
ARM920T I/O
AMBA
ASB
GCLK
bus
Rest of ARM920T
interface
nF, iA
FCLK
Figure 5-1. ARM920T Clocking
5-1

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