s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 317

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
UART TX/RX STATUS REGISTER
There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block.
Transmitter empty
Transmit buffer empty
Receive buffer data ready
UTRSTAT0
UTRSTAT1
UTRSTAT2
Register
UTRSTATn
0x50000010
0x50004010
0x50008010
Address
Bit
[2]
[1]
[0]
Set to 1 automatically when the transmit buffer register has
no valid data to transmit and the transmit shift register is
empty.
0 = Not empty
1 = Transmitter (transmit buffer & shifter register) empty
Set to 1 automatically when transmit buffer register is empty.
0 =The buffer register is not empty
1 = Empty
If the UART uses the FIFO, users should check Tx FIFO
Count bits and Tx FIFO Full bit in the UFSTAT register
instead of this bit.
Set to 1 automatically whenever receive buffer register
contains valid data, received over the RXDn port.
0 = Empty
1 = The buffer register has a received data
If the UART uses the FIFO, users should check Rx FIFO
Count bits and Rx FIFO Full bit in the UFSTAT register
instead of this bit.
(In Non-FIFO mode, Interrupt or DMA is requested.
In FIFO mode, Interrupt or DMA is requested, when Tx
FIFO Trigger Level is set to 00 (Empty))
(In Non-FIFO mode, Interrupt or DMA is requested)
R/W
R
R
R
UART channel 0 Tx/Rx status register
UART channel 1 Tx/Rx status register
UART channel 2 Tx/Rx status register
Description
Description
Reset Value
Initial State
0x6
0x6
0x6
1
1
0
11-15
UART