vt82c586a ETC-unknow, vt82c586a Datasheet - Page 22

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

Register Descriptions
VIA-Specific I/O Ports
A8/A9 is a VIA-legacy I/O index/data pair. Chipset registers
in earlier VIA chipsets were accessed using this mechanism.
These registers are the only remaining functions accessed in
this way (norte: in future ACPI-capable versions of the
82C586A chip, access to these functions will be defined by
ACPI so the A8/A9 mechanism will no longer be used).
These functions are accessed by writing the indicated offset
(C8h or C9h) to I/O port A8h then writing the desired data to
I/O port A9h.
Port A8/A9 Offset C8h - General Purpose Output Port 0
These bits are controlled by PCW0 for latching data in an
external 373 latch. A 1-0-1 pulse is generated on PCW0 when
this port is written and the contents of this register appear on
the indicated bits of the ISA SD bus.
Port A8/A9 Offset C9h - General Purpose Output Port 1
These bits are controlled by PCW1 for latching data in an
external 373 latch. A 1-0-1 pulse is generated on PCW1 when
this port is written and the contents of this register appear on
the indicated bits of the ISA SD bus.
Preliminary Revision 0.1 October 13, 1996
7-0
7-0
SD15-8
SD15-8

-16-
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only.
actions and programming of these registers are included in
numerous
information here is beyond the scope of this document). All of
these registers reside in I/O space.
Port 61 - Misc Functions & Speaker Control ................. RW
Port 92h - System Control ................................................ RW
7-6
5-4
7
6
5
4
3
2
1
0
3
2
1
0
Reserved
IOCHCK# Active .................................................RO
This bit is set when the ISA bus IOCHCK# signal is
asserted. Once set, this bit may be cleared by setting
bit-3 of this register.
enable recording of the next IOCHCK#. IOCHCK#
generates NMI to the CPU if NMI is enabled.
Timer/Counter 2 Output......................................RO
This bit reflects the output of Timer/Counter 2
without any synchronization.
Refresh Detected...................................................RO
This bit toggles on every rising edge of the ISA bus
REFRESH# signal.
IOCHCK# Disable...............................................RW
Reserved
Speaker Enable ....................................................RW
Timer/Counter 2 Enable .....................................RW
Hard Disk Activity LED Status
Reserved
Power-On Password Bytes Inaccessable ..default=0
Reserved
A20 Address Line Enable
High Speed Reset
1-3 On
0
1
0
1
0
1
0
0
1
0
1
industry
Enable IOCHCK# assertions ................. default
Force IOCHCK# inactive and clear any
“IOCHCK# Active” condition in bit-6
Disable................................................... default
Enable Timer/Ctr 2 output to drive SPKR pin
Disable................................................... default
Enable Timer/Counter 2
Off
A20 disabled / forced 0 (real mode) ...... default
A20 address line enabled
Normal
Briefly pulse system reset to switch from
protected mode to real mode
........................................ always reads 0
........................................RW, default=0
.................................................... default
........................................ always reads 0
........................................ always reads 0
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Detailed descriptions of the
Bit-3 should be cleared to
(duplication
Register Descriptions
VT82C586A
of
that