vt82c586a ETC-unknow, vt82c586a Datasheet - Page 26

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

Interrupt Controller Registers
Ports 20-21 - Master Interrupt Controller
The Master Interrupt Controller controls system interrupt
channels 0-7.
Controller. They are:
I/O Address Bits 15-0
0000 0000 001x xxx0
0000 0000 001x xxx1
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Controller
The Slave Interrupt Controller controls system interrupt
channels 8-15.
occupies two register locations:
I/O Address Bits 15-0
0000 0000 101x xxx0
0000 0000 101x xxx1
Note that not all address bits are decoded.
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Preliminary Revision 0.1 October 13, 1996

Two registers control the Master Interrupt
The slave system interrupt controller also
Register Name
Register Name
Master Interrupt Control
Master Interrupt Mask
Slave Interrupt Control
Slave Interrupt Mask
RW
RW
RW
RW
-20-
Interrupt Controller Shadow Registers
The following shadow registers are enabled by setting bit 4 of
Rx47 to 1 (offset 47h in the PCI-ISA Bridge function 0
register group). If the shadow registers are enabled, they are
read back at the indicated I/O port instead of the standard
interrupt controller registers (writes to the interrupt controller
register ports are directed to the standard interrupt controller
registers).
Port 20 - Master Interrupt Control Shadow ................... RO
Port 21 - Master Interrupt Mask Shadow ....................... RO
Port A0 - Slave Interrupt Control Shadow ..................... RO
Port A1 - Slave Interrupt Mask Shadow ........................ RO
7-5
7-5
4-0
7-5
7-5
4-0
4
3
2
1
0
4
3
2
1
0
Reserved
OCW3 bit 5
OCW2 bit 7
ICW4 bit 4
ICW4 bit 1
ICW1 bit 3
Reserved
T7-T3 of Interrupt Vector Address
Reserved
OCW3 bit 5
OCW2 bit 7
ICW4 bit 4
ICW4 bit 1
ICW1 bit 3
Reserved
T7-T3 of Interrupt Vector Address
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
........................................ always reads 0
Register Descriptions
VT82C586A