M29DW128F60NF1 STMICROELECTRONICS [STMicroelectronics], M29DW128F60NF1 Datasheet - Page 17

• Manufacturer Part Number: M29DW128F60NF1
• Description: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M29DW128F
3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are Bus Read (Random
and Page modes), Bus Write, Output Disable, Standby and Automatic Standby.
Dual operations are possible in the M29DW128F, thanks to its multiple bank architecture. While
programming or erasing in one banks, read operations are possible in any of the other banks.
Write operations are only allowed in one bank at a time.
See
Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the
memory and do not affect bus operations.
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. To speed up the read operation the memory array can be read in Page mode where
data is internally read and stored in a page buffer. The Page has a size of 8 Words and is
addressed by the address inputs A0-A2.
A valid Bus Read operation involves setting the desired address on the Address Inputs,
applying a Low signal, V
V
Waveforms,
details of when the output becomes valid.
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip
Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
the whole Bus Write operation. See
Table 27
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
pins are placed in the high-impedance state. To reduce the Supply Current to the Standby
Supply Current, I
level see
continue to use the Program/Erase Supply Current, I
the operation completes.
IH
. The Data Inputs/Outputs will output the value, see
Table 3
and
Table 25: DC
and
Figure 13: Page Read AC
Table
Table
CC2
28, Write AC Characteristics, for details of the timing requirements.
, Chip Enable should be held within V
6, Bus Operations, for a summary. Typically glitches of less than 5ns on
Characteristics. During program or erase operations the memory will
IL
, to Chip Enable and Output Enable and keeping Write Enable High,
IH
, the memory enters Standby mode and the Data Inputs/Outputs
Figure 14
Waveforms, and
and
Figure
CC3
Figure 12: Random Read AC
Table 26: Read AC
, for Program or Erase operations until
15, Write AC Waveforms, and
CC
± 0.2V. For the Standby current
Characteristics, for
3 Bus operations
IH
, during
IH
17/93
.