M29DW128F60NF1 STMICROELECTRONICS [STMicroelectronics], M29DW128F60NF1 Datasheet - Page 34

• Manufacturer Part Number: M29DW128F60NF1
• Description: 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V Supply, Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

6 Command Interface
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
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The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during
a Write to Buffer and Program operation.
If is not possible to detect Program operation fails when changing programmed data from ‘0’ to
‘1’, that is when reprogramming data in a portion of memory already programmed. The
resulting data will be the logical OR between the previous value and the current value.
A Write to Buffer and Program Abort and Reset command must be issued to abort the Write to
Buffer and Program operation and reset the device in Read mode.
During Write to Buffer and Program operations, the bank being programmed will accept
Program/Erase Suspend commands.
See
suggested flowchart on using the Write to Buffer and Program command.
Write to Buffer and Program Confirm command
The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and
Program command and to program the n+1 Words loaded in the Write Buffer by this command.
Write to Buffer and Program Abort and Reset command
The Write to Buffer and Program Abort and Reset command is used to abort Write to Buffer
and Program command.
Double Word Program command
This is used to write two adjacent Words in x16 mode, simultaneously. The addresses of the
two Words must differ only in A0.
Three bus write cycles are necessary to issue the command:
1.
2.
3.
Quadruple Word Program command
This is used to write a page of four adjacent Words, in x16 mode, simultaneously. The
addresses of the four Words must differ only in A1 and A0.
Five bus write cycles are necessary to issue the command:
1.
2.
3.
4.
5.
Double Byte Program Command
This is used to write two adjacent Bytes in x8 mode, simultaneously. The addresses of the two
Bytes must differ only in DQ15A-1.
Appendix
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Word to be written.
The third bus cycle latches the Address and the Data of the second Word to be written and
starts the Program/Erase Controller.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Word to be written.
The third bus cycle latches the Address and the Data of the second Word to be written.
The fourth bus cycle latches the Address and the Data of the third Word to be written.
The fifth bus cycle latches the Address and the Data of the fourth Word to be written and
starts the Program/Erase Controller.
E,
Figure 27: Write to Buffer and Program Flowchart and Pseudo
M29DW128F
Code, for a